FXLS8471Q datasheet(16/75 Pages) FREESCALE

16 / 75 page

FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

Digital Interfaces

6.1

I2C interface characteristics

Figure 5. I2C slave timing diagram

Table 7. I2C slave timing values(1)

1. All values referred to VIH (min) and VIL (max) levels.

Parameter

Symbol

I2C Fast Mode

Unit

Min

Max

SCL Clock Frequency

fSCL

400

kHz

Bus Free Time between STOP and START condition

tBUF

1.3

μs

(Repeated) START Hold Time

tHD;STA

0.6

μs

(Repeated) START Setup Time

tSU;STA

0.6

μs

STOP Condition Setup Time

tSU;STO

0.6

μs

SDA Data Hold Time

tHD;DAT

0.05

0.9(2)

2. This device does not stretch the LOW period (tLOW) of the SCL signal.

μs

SDA Valid Time(3)

3. tVD;DAT = time for Data signal from SCL LOW to SDA output.

tVD;DAT

0.9(2)

μs

SDA Valid Acknowledge Time(4)

4. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;ACK

0.9(2)

μs

SDA Setup Time

tSU;DAT

100

SCL Clock Low Time

tLOW

1.3

μs

SCL Clock High Time

tHIGH

0.6

μs

SDA and SCL Rise Time

20 + 0.1 Cb

(5)

5. Cb = total capacitance of one bus line in pF.

300

SDA and SCL Fall Time

20 + 0.1 Cb

(5)

300

Pulse width of spikes on SDA and SCL that must be suppressed by

internal input filter

tSP

050

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MSC610

tSU;STO

tSU;STA

tHD;STA

tHIGH

tLOW

tSU;DAT

tHD;DAT

SDA

SCL

tBUF

tSP

tHD;STA

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