FXLS8471Q datasheet(33/75 Pages) FREESCALE

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FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

The active bit selects between Standby mode and Active mode. The default value is 0 (Standby mode) on reset.

The lnoise bit selects between normal full dynamic range mode and a high sensitivity, low-noise mode. In low-noise mode the

maximum signal that can be measured is ±4 g. Note: Any thresholds set above 4 g will not be reached.

The f_read bit selects between normal and fast-read modes where the auto-increment counter will also skip over the LSB data

bytes when f_read = 1. All of the acceleration data MSB’s can be read out with a single 3-byte burst read starting at the

OUT_X_MSB register when f_read = 1.

NOTE

The f_read bit can only be changed while F_SETUP[f_mode] = 0.

10.1.9

CTRL_REG2 (0x2B) register

Table 31. System Output Data Rate selection

dr2

dr1

dr0

ODR (Hz)

Period (ms)

800.0

1.25

400.0

2.5

200.0

100.0

100

50.0

101

12.5

6.25

160

1.5625

640

Table 32. CTRL_REG2 register

rst

—

smods[1:0]

slpe

mods[1:0]

000000

Table 33. CTRL_REG2 bit descriptions

Field

Description

The st bit activates the accelerometer self-test function. When st is set to 1, a change will occur in the device output levels for

each axis, allowing the host application to check the functionality of the transducer and measurement signal chain.

Self-Test Enable:

0: Self-Test disabled

1: Self-Test enabled.

rst

The rst bit is used to initiate a software reset. The reset mechanism can be enabled in both Standby and Active modes. When the

rst bit is set, the boot mechanism resets all functional block registers and loads the respective internal registers with their default

values. Note that the current revision of FXLS8471Q silicon, as identified by a WHO_AM_I value of 0x6A, has an errata

associated with the software reset mechanism when the device is operated in SPI mode. Refer to Appendix A.1 for further

information and a suggested work-around. After setting the rst bit, the system will automatically transition to Standby mode.

Therefore, if the system was already in Standby mode, the reboot process will immediately begin; else if the system was in Active

mode the boot mechanism will automatically transition the system from Active mode to Standby mode, only then can the reboot

process begin. A system reset can also be initiated by pulsing the external RST pin high.

The I2C and SPI communication systems are also reset to avoid corrupted data transactions. The host application should allow

1 ms between issuing a software (setting rst bit) or hardware (pulsing RST pin) reset and attempting communications with the

device over the I2C or SPI interfaces. When the SPI interface mode is desired and multiple devices are present on the bus, make

sure that the bus is quiet (all slave device MISO pins are high-z) during this 1 ms period to ensure the device does not

inadvertently enter I2C mode. See Section 6.2.3 for further information about the interface mode auto-detection circuit.

At the end of the boot process, the rst bit is hardware cleared.

0: Device reset disabled

1: Device reset enabled.

smods[1:0] Sleep mode power scheme selection. See Table 34 for more information.

slpe(1)

1. When SLPE = 1, a transition between Sleep mode and Wake mode results in a FIFO flush and a reset of internal functional block counters.

All functional block status information is preserved except where otherwise indicated. For further information, refer to the CTRL_REG3 register

description (fifo_gate bit).

Auto-Sleep mode enable:

0: Auto-Sleep is not enabled

1: Auto-Sleep is enabled.

mods[1:0]

Accelerometer OSR selection. This setting, along with the ODR selection determines the Active mode power and RMS noise for

acceleration measurements. See Table 34 for more information.

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