FXLS8471Q datasheet(56/75 Pages) FREESCALE

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FXLS8471Q

Sensors

Freescale Semiconductor, Inc.

10.9.2

A_VECM_THS_MSB (0x60) register

10.9.3

A_VECM_THS_LSB (0x61) register

10.9.4

A_VECM_CNT (0x62) register

The debounce timer period is determined by the ODR selected in CTRL_REG1; it is equal to the number indicated in

A_VECM_CNT register times 1/ODR. For example, a value of 16 in A_VECM_CNT with an ODR setting of 400 Hz will result in

a debounce period of 40 ms.

Table 92. A_VECM_THS_MSB register

a_vecm_dbcntm

—

a_vecm_ths[12:8]

5’b00000

Table 93. A_VECM_THS_MSB bit descriptions

Field

Description

a_vecm_dbcntm

Control bit a_vecm_dbcntm defines how the debounce timer is reset when the condition for triggering the interrupt is

no longer true.

When a_vecm_dbcntm = 0 the debounce counter is decremented by 1 when the vector-magnitude result is below the

programmed threshold value.

When a_vecm_dbcntm = 1 the debounce counter is cleared when the vector-magnitude result is below the

programmed threshold value.

a_vecm_ths[12:8]

Five MSBs of the 13-bit unsigned A_VECM_THS value. The resolution is equal to the selected accelerometer

resolution set in XYZ_DATA_CFG[fs]

Table 94. A_VECM_THS_LSB register

a_vecm_ths[7:0]

8’b00000000

Table 95. A_VECM_CNT register

a_vecm_cnt[7:0]

8’b00000000

Table 96. A_VECM_CNT bit description

Field

Description

a_vecm_cnt[7:0]

Vector-magnitude function debounce count value.

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