PIC16F628-20SLASHSS datasheet(99/160 Pages) MICROCHIP

99 / 160 page

Preliminary

DS40300B-page 99

PIC16F62X

14.2.6

INTERNAL 4 MHZ OSCILLATOR

The internal RC oscillator provides a fixed 4 MHz (nom-

inal) system clock at Vdd = 5V and 25

°C, see “Electrical

Specifications” section for information on variation over

voltage and temperature.

14.2.7

CLKOUT

The PIC16F62X can be configured to provide a clock

out signal by programming the configuration word. The

oscillator frequency, divided by 4 can be used for test

purposes or to synchronize other logic.

14.3

Special Feature: Dual Speed

Oscillator Modes

A software programmable dual speed oscillator mode

is provided when the PIC16F62X is configured in either

ER or INTRC oscillator modes. This feature allows

users to dynamically toggle the oscillator speed

between 4MHz and 37kHz. In ER mode, the 4MHz set-

ting will vary depending on the size of the external

resistor. Also in ER mode, the 37kHz operation is fixed

and does not vary with resistor size. Applications that

require low current power savings, but cannot tolerate

putting the part into sleep, may use this mode.

The OSCF bit in the PCON register is used to control

dual speed mode. See Section 4.2.2.6, Figure 4-9.

14.4

Reset

The PIC16F62X differentiates between various kinds

of reset:

Power-on reset (POR)

MCLR reset during normal operation

MCLR reset during SLEEP

WDT reset (normal operation)

WDT wake-up (SLEEP)

Brown-out Detect (BOD)

Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any

other reset. Most other registers are reset to a “reset

state” on Power-on reset, MCLR reset, WDT reset and

MCLR reset during SLEEP. They are not affected by a

WDT wake-up, since this is viewed as the resumption

of normal operation. TO and PD bits are set or cleared

differently in different reset situations as indicated in

Table 14-4. These bits are used in software to deter-

mine the nature of the reset. See Table 14-7 for a full

description of reset states of all registers.

A simplified block diagram of the on-chip reset circuit is

shown in Figure 14-8.

The MCLR reset path has a noise filter to detect and

ignore small pulses. See Table 12-6 for pulse width

specification.

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