PIC16F628-20SLASHSS datasheet(11/160 Pages) MICROCHIP

11 / 160 page

Preliminary

DS40300B-page 11

PIC16F62X

TABLE 3-1:

PIC16F62X PINOUT DESCRIPTION

Name

DIP/

SOIC

Pin #

SSOP

Pin #

I/O/P

Type

Buffer

Type

Description

RA0/AN0

I/O

Bi-directional I/O port/Analog comparator input

RA1/AN1

I/O

Bi-directional I/O port/Analog comparator input

RA2/AN2/VREF

I/O

Bi-directional I/O port/Analog comparator input/VREF out-

put

RA3/AN3/CMP1

I/O

Bi-directional I/O port/Analog comparator input/compara-

tor output

RA4/T0CKI/CMP2

I/O

Bi-directional I/O port/Can be configured as T0CKI/com-

parator output

RA5/MCLR/THV

Input port/master clear (reset input/programming voltage

input. When configured as MCLR, this pin is an active low

reset to the device. Voltage on MCLR/THV must not

exceed VDD during normal device operation.

RA6/OSC2/CLKOUT

I/O

Bi-directional I/O port/Oscillator crystal output. Connects

to crystal or resonator in crystal oscillator mode. In ER

mode, OSC2 pin outputs CLKOUT which has 1/4 the fre-

quency of OSC1, and denotes the instruction cycle rate.

RA7/OSC1/CLKIN

I/O

Bi-directional I/O port/Oscillator crystal input/external

clock source input. ER biasing pin.

RB0/INT

I/O

TTL/ST(1)

Bi-directional I/O port/external interrupt. Can be software

programmed for internal weak pull-up.

RB1/RX/DT

I/O

TTL/ST

(3)

Bi-directional I/O port/ USART receive pin/synchronous

data I/O. Can be software programmed for internal weak

pull-up.

RB2/TX/CK

I/O

TTL/ST

(3)

Bi-directional I/O port/ USART transmit pin/synchronous

clock I/O. Can be software programmed for internal weak

pull-up.

RB3/CCP1

I/O

TTL/ST

(4)

Bi-directional I/O port/Capture/Compare/PWM I/O. Can

be software programmed for internal weak pull-up.

RB4/PGM

I/O

TTL/ST

(5)

Bi-directional I/O port/Low voltage programming input pin.

Wake-up from SLEEP on pin change. Can be software

programmed for internal weak pull-up. When low voltage

programming is enabled, the interrupt on pin change and

weak pull-up resistor are disabled.

RB5

I/O

TTL

Bi-directional I/O port/Wake-up from SLEEP on pin

change. Can be software programmed for internal weak

pull-up.

RB6/T1OSO/T1CKI

I/O

TTL/ST

(2)

Bi-directional I/O port/Timer1 oscillator output/Timer1

clock input. Wake up from SLEEP on pin change. Can be

software programmed for internal weak pull-up.

RB7/T1OSI

I/O

TTL/ST

(2)

Bi-directional I/O port/Timer1 oscillator input. Wake up

from SLEEP on pin change. Can be software programmed

for internal weak pull-up.

VSS

55,6

—

Ground reference for logic and I/O pins.

VDD

15,16

—

Positive supply for logic and I/O pins.

Legend:

O = output

I/O = input/output

P = power

— = Not used

I = Input

ST = Schmitt Trigger input

TTL = TTL input

I/OD =input/open drain output

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.

Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode.

Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode.

Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode.

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