PIC16F628-20SLASHSS datasheet(78/160 Pages) MICROCHIP

78 / 160 page

PIC16F62X

DS40300B-page 78

Preliminary

12.2

USART Asynchronous Mode

In this mode, the USART uses standard nonreturn-to-

zero (NRZ) format (one start bit, eight or nine data bits

and one stop bit). The most common data format is

8-bits. An on-chip dedicated 8-bit baud rate generator

can be used to derive standard baud rate frequencies

from the oscillator. The USART transmits and receives

the LSb first. The USART’s transmitter and receiver are

functionally independent but use the same data format

and baud rate. The baud rate generator produces a

clock either x16 or x64 of the bit shift rate, depending

on bit BRGH (TXSTA<2>). Parity is not supported by

the hardware, but can be implemented in software (and

stored as the ninth data bit). Asynchronous mode is

stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the fol-

lowing important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

12.2.1

USART ASYNCHRONOUS TRANSMITTER

The USART transmitter block diagram is shown in

Figure 12-5. The heart of the transmitter is the transmit

(serial) shift register (TSR). The shift register obtains its

data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXREG register is empty and

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will reset only when new data is loaded into the

TXREG register. While flag bit TXIF indicated the sta-

tus of the TXREG register, another bit TRMT

(TXSTA<1>) shows the status of the TSR register. Sta-

tus bit TRMT is a read only bit which is set when the

TSR register is empty. No interrupt logic is tied to this

bit, so the user has to poll this bit in order to determine

if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the baud rate generator (BRG) has produced a

shift clock (Figure 12-5). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally when transmission

is first started, the TSR register is empty, so a transfer

to the TXREG register will result in an immediate trans-

fer to TSR resulting in an empty TXREG. A back-to-

back transfer is thus possible (Figure 12-7). Clearing

enable bit TXEN during a transmission will cause the

transmission to be aborted and will reset the transmit-

ter. As a result the RB2/TX/CK pin will revert to hi-

impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG reg-

ister. This is because a data write to the TXREG regis-

ter can result in an immediate transfer of the data to the

TSR register (if the TSR is empty). In such a case, an

incorrect ninth data bit maybe loaded in the TSR regis-

ter.

Note 1: The TSR register is not mapped in data

memory so it is not available to the user.

Note 2: Flag bit TXIF is set when enable bit TXEN

is set.

FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM

TXIF

TXIE

Interrupt

TXEN

Baud Rate CLK

SPBRG

Baud Rate Generator

TX9D

MSb

LSb

Data Bus

TXREG register

TSR register

(8)

TX9

TRMT

SPEN

RB2/TX/CK pin

Pin Buffer

and Control

• • •

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