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PIC16F628-20/SS датащи(PDF) 18 Page - Microchip Technology |
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PIC16F628-20/SS датащи(HTML) 18 Page - Microchip Technology |
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18 / 160 page ![]() PIC16F62X DS40300B-page 18 Preliminary © 1999 Microchip Technology Inc. TABLE 4-4: SPECIAL FUNCTION REGISTERS SUMMARY BANK3 Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets(1) Bank 1 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg- ister) xxxx xxxx xxxx xxxx 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000 183h STATUS IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 184h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 185h Unimplemented — — 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111 187h Unimplemented — — 188h Unimplemented — — 189h Unimplemented — — 18Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Note 1: Other (non power-up) resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during normal operation. |
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