PIC16F628-20SLASHSS datasheet(80/160 Pages) MICROCHIP

80 / 160 page

PIC16F62X

DS40300B-page 80

Preliminary

12.2.2

USART ASYNCHRONOUS RECEIVER

The receiver block diagram is shown in Figure 12-8.

The data is received on the RB1/RX/DT pin and drives

the data recovery block. The data recovery block is

actually a high speed shifter operating at x16 times the

baud rate, whereas the main receive serial shifter oper-

ates at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setting bit CREN (RCSTA<4>).

The heart of the receiver is the receive (serial) shift reg-

ister (RSR). After sampling the STOP bit, the received

data in the RSR is transferred to the RCREG register (if

it is empty). If the transfer is complete, flag bit RCIF

(PIR1<5>) is set. The actual interrupt can be enabled/

disabled by setting/clearing enable bit RCIE (PIE1<5>).

Flag bit RCIF is a read only bit which is cleared by the

hardware. It is cleared when the RCREG register has

been read and is empty. The RCREG is a double buff-

ered register, i.e. it is a two deep FIFO. It is possible for

two bytes of data to be received and transferred to the

RCREG FIFO and a third byte begin shifting to the RSR

byte, if the RCREG register is still full then overrun error

bit OERR (RCSTA<1>) will be set. The word in the RSR

will be lost. The RCREG register can be read twice to

retrieve the two bytes in the FIFO. Overrun bit OERR

has to be cleared in software. This is done by resetting

the receive logic (CREN is cleared and then set). If bit

OERR is set, transfers from the RSR register to the

RCREG register are inhibited, so it is essential to clear

error bit OERR if it is set. Framing error bit FERR

(RCSTA<2>) is set if a stop bit is detected as clear. Bit

FERR and the 9th receive bit are buffered the same

way as the receive data. Reading the RCREG, will load

bits RX9D and FERR with new values, therefore it is

essential for the user to read the RCSTA register before

reading RCREG register in order not to lose the old

FERR and RX9D information.

FIGURE 12-8: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RB1/RX/DT

Pin Buffer

and Control

SPEN

Data

Recovery

CREN

OERR

FERR

RSR register

MSb

LSb

RX9D

RCREG register

FIFO

Interrupt

RCIF

RCIE

Data Bus

÷ 64

÷ 16

Stop

Start

(8)

RX9

• • •

RX9

ADEN

RX9

ADEN

RSR<8>

Enable

Load of

Receive

Buffer

RCREG register

RX9D

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