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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MIC74 датащи(PDF) 5 Page - Micrel Semiconductor |
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MIC74 датащи(HTML) 5 Page - Micrel Semiconductor |
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5 / 20 page  August 1, 2000 5 MIC74 MIC74 Micrel Register Descriptions Device Configuration Register G F C _ V E D ] 7 [ D] 6 [ D] 5 [ D] 4 [ D] 3 [ D] 2 [ D] 1 [ D] 0 [ D . o r e z s a e t i r w s y a w l AN A FE I Power-On Default Value: 0000 0000 b, 00h Interrupts disabled Not in Fan Mode Command_byte addess: 0000 0000 b, 00h Type: 8-bits, read/write Bit Name: IE Function: Global interrupt enable. Operation: 1 = enabled 0 = disabled Bit Name: FAN Function: Selects Fan Mode (P[7:4] vs. /FS[2:0], /SHDN) Operation: 1 = Fan Mode 0 = I/O Mode Bit Name: D[2] through D[6] Function: Reserved Operation: Reserved—always write as zero Data Direction Register R I D ] 7 [ D] 6 [ D] 5 [ D] 4 [ D] 3 [ D] 2 [ D] 1 [ D] 0 [ D 7 R I D6 R I D5 R I D4 R I D3 R I D2 R I D1 R I D0 R I D Power-On Default Value: 0000 0000 b, 00h all P n’s configured as inputs Command_byte addess: 0000 0001 b, 01h Type: 8-bits, read/write Bit Name: DIR n Function: Selects data direction, input or output, of P n Operation: 1 = output 0 = input Notes: If Fan Mode is selected, that is, the FAN bit of the DEV_CFG register is set to one, P[7:4] are automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and /SHDN. The DIR register has no effect on these I/O bits while in Fan Mode. Output Configuration Register G F C _ T U O ] 7 [ D] 6 [ D] 5 [ D] 4 [ D] 3 [ D] 2 [ D] 1 [ D] 0 [ D 7 T U O6 T U O5 T U O4 T U O3 T U O2 T U O1 T U O0 T U O Power-On Default Value: 0000 0000 b, 00h all outputs open-drain Command_byte addess: 0000 0010 b, 02h Type: 8-bits, read/write Bit Name: OUT n Function: Selects output driver configuration of P n when P n is configured as an output. Operation: 1 = push-pull 0 = open-drain Notes: If Fan Mode is selected, that is, the FAN bit of the DEV_CFG register is set to one, P[7:4] are automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and /SHDN. The OUT_CFG register has no effect on these I/O bits while in Fan Mode. Status Register S U T A T S ] 7 [ D] 6 [ D] 5 [ D] 4 [ D] 3 [ D] 2 [ D] 1 [ D] 0 [ D 7 S6 S5 S4 S3 S2 S1 S0 S Power-On Default Value: 0000 0000 b, 00h no interrupts pending Command_byte addess: 0000 0011 b, 03h Type: 8-bits, read only Bit Name: S n Function: Flag for Pn input-change event when P n is configured as an input; S n is set when the corresponding input changes state. Operation: 1 = change occured 0 = no change occured Notes: If Fan Mode is selected, that is, the FAN bit of the DEV_CFG register is set to one, P[7:4] are automatically configured as open-drain outputs. They are then referred to as /FS[2:0] and /SHDN. No interrupts of any kind are generated by these pins while in Fan Mode. All status bits are cleared after any read operation is performed on STATUS. |
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