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MIC74 датащи(PDF) 11 Page - Micrel Semiconductor |
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MIC74 датащи(HTML) 11 Page - Micrel Semiconductor |
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11 / 20 page ![]() August 1, 2000 11 MIC74 MIC74 Micrel S 00011001 A 0100 A2 A1 A0 0/A P Alert Response Address (master requests address of interupting device) P0* /ALERT Slave Address (interrupting MIC74 announces its address) Master-to-slave transmission Slave-to-master response STOP ACKNOWLEDGE R/W = READ NOT ACKNOWLEDGE t/INT t/IR * Assumes P0 interrupts properly configured and enabled. P0 used as an example. Timing for P1 to P7 is identical. Figure 7. Interrupt Handling Using the Alert Response Address /A P S 0001 A2 A1 A0 0 A 000000 XXXXXXXX 11 A A Slave Address (host addresses an MIC74) P0* /ALERT Command Byte (03h = selects status register) Status Value† (MIC74 sends status) Slave Address (host addresses an MIC74) Master-to-slave transmission Slave-to-master response ACKNOWLEDGE R/W = WRITE S 0001 A2 A1 A0 1 R/W = READ STOP NOT ACKNOWLEDGE t/INT t/R * Assumes P0 interrupts properly configured and enabled. P0 used as an example. Timing for P1 to P7 is identical. † STATUS register is cleared to zero following this operation. ACKNOWLEDGE ACKNOWLEDGE Figure 8. Interrupt Handling Without the Alert Response Address |
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