MIC74 datasheet(10/20 Pages) MICREL

10 / 20 page

MIC74

Micrel

MIC74

August 1, 2000

Applications Information

Bit Transfer

The data received on the DATA pin must be stable during the

high period of the clock.

DATA

CLK

Data Change Allowed

Data Stable,

Data Valid

Figure 3. Acceptable Bit Transfer Conditions

Data can change state only when the CLK line is low. Refer

to Figure 3.

Start and Stop Conditions

Two unique bus situations define “start” and “stop” condi-

tions. A high-to-low transition of the DATA line while CLK is

high indicates a start condition. A low-to-high transition of the

DATA line while CLK is high defines a stop condition. See

Figure 4.

DATA

CLK

Start

StoP

Figure 4. Start and Stop Definitions

Start (S) and stop (P) conditions are always generated by the

bus master (host). After a start condition, the bus is consid-

ered to be busy. The bus becomes free again after a certain

time following a stop condition or after both CLK and DATA

lines remain high for more than 50

µs.

Serial Byte Format

Every byte consists of 8 bits. Each byte transferred on the bus

must be followed by an acknowledge bit. Bytes are trans-

ferred with the MSB (most significant bit) first. See

Figure 5.

Acknowledge and Not Acknowlege

The acknowledge related clock pulse is generated by the

master. The transmitter releases the DATA line (high) during

the acknowledge clock cycle.

In order to acknowledge (ACK) a byte, the receiver must pull

the DATA line low during the high period of the clock pulse

according the bus timing specifications. A slave device that

wishes to not acknowledge a byte must let the DATA line

remain high during the acknowledge clock pulse. See Fig-

ure 6.

123456789

ACK

MSB

LSB

NAK (high)

ACK (low)

DATA

(Host)

CLK

DATA

(Slave MIC74)

Figure 6. Acknowledge and Not Acknowledge

123456789

ACK

MSB

LSB

DATA

CLK

Byte Complete

Start

StoP

Figure 5. Serial Byte Format

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