AN2014 datasheet(51/65 Pages) STMICROELECTRONICS

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AN2014

Power supply loss and application reset

6.1.2

SPI family

Main recommendation for protecting an SPI transaction is to deselect the device in a safe

way. The chip must be deselected taking care of the timings of Chip Select respect to the

Clock rising edge.

•

Smart connections of EEPROM pins help to avoid deselect timing violation (tCHSL and

tCHSH) when Master releases SPI bus. Refer to Section 4: Hardware considerations

section for safe recommendations. At deselect, EEPROM will go into the standby state

(see Figure 41: SPI bus enters the high impedance state (Master reset)).

•

However, a write cycle may be triggered if the EEPROM is deselected between two

data bytes of a write instruction. On 4-Kbit or lower-density SPI device, setting the W

pin to Low before deselecting the memory will prevent the write cycle execution.

•

When the Master restarts, it must run a data polling sequence to check that the

EEPROM is ready (and that no write cycle is in progress). Refer to Section 5.2: Optimal

Write control.

•

As soon as the SPI device is ready, a WRDI instruction must be issued if the WEL bit in

the Status Register is still set to 1. In so doing, the device is protected against any

parasitic write instruction.

These recommendations will maximize the control on the EEPROM in case of inadvertent

Master reset. Recommendations for Master restart can also be the default sequence each

time Master comes out of the reset state like after Power up.

Figure 41. SPI bus enters the high impedance state (Master reset)

1. A pull-down resistor on C prevents any tSHCH timing violation (as a pull-up resistor on C causes C and S to

rise at the same time, inducing tSHCH = 0).

Ai11091c

Safe

SPI bus connections

SPI bus waveforms when the bus enters

the high-impedance state

Safe

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