AN2014 datasheet(37/65 Pages) STMICROELECTRONICS

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AN2014

Software considerations

The purpose of the suggestions presented below is to help the application designers make

the most of ST’s EEPROM products, and to help to improve the system robustness and

compatibility with future EEPROM devices.

5.1

EEPROM electrical parameters

Low-level drivers (hardware dependent) must follow the EEPROM electrical parameters for

correct communication. EEPROM samples are not absolute references for software

validation as they are not representative of production variations. The EEPROM timings

given in the device datasheets are unique reference characteristics. They correspond to

minimum and maximum timing values to be taken into account for hardware and software

calibration.

Typical errors to be avoided in applications are:

•

Input voltage levels not compatible with the specifications, VIL<0.3VCC and

VIH > 0.7VCC.

•

Excessive current requested from EEPROM data output buffer (output CMOS levels

are no more guaranteed).

•

Write time not completed (tW = 5 ms) before issuing a new command.

•

Data setup time in applications using high clock rate or very smooth waveforms with

slow transitions (as a general recommendation, signal rise and fall time must be less

than 10% of the clock period).

•

Out of specification (too short) pulses on the Clock signal, Chip select signal or on

Start/Stop conditions.

The behavior of EEPROM devices operating “out of specification” can never be guaranteed

and is not always predictable. Moreover, major compatibility issues may arise when

switching to a new device version or using a compatible device from another supplier. When

using a double source supplier for EEPROMs, the worst value of each single timing should

be used as a reference for direct compatibility.

5.2

Optimal Write control

EEPROM devices are simple products with few operating modes and instructions. It is

nevertheless worth focusing on the features that can be used to improve performance and

application robustness.

5.2.1

Page mode

The memory array is divided into pages. The size of a page is given on the first page of the

product datasheet (it can be 8, 16, 32, 64, 128 or 256 bytes).

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