AN4253 datasheet(41/44 Pages) STMICROELECTRONICS

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DocID024255 Rev 2

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AN4253

asm examples

e_lis

r0, ME_MCTL_DRUN_R2@h

e_or2i

r0, ME_MCTL_DRUN_R2@l

e_stw

r0, ME_REG_MCTL (r7)

// 2. step - inverted key

// wait for transition to complete (test of GS.MTRANS bit)

me_wait_sysclk:

e_lwz

r0, ME_REG_GS (r7)

// read GS register

se_btsti r0, ME_GS_MTRANS

// test the MTRANS bit

se_bc

0,2,me_wait_pll0on

// if '1' > wait in loop

// check that system clock is FMPLL0

e_and2i. r0, ME_GS_SYSCLK_MASK

// get system clock status

se_cmpi

r0, ME_MC_SYSCLK_PLL

// check the value

se_bc

1,2,clk_startup_end

// continue if PLL is the system clock

clk_fault_handler:

se_b .

// fault handler loop, app code needed

clk_startup_end:

A.12

Software Watchdog Timer (SWT) disable

e_lis

r7, SWT_BASE@h

e_or2i

r7, SWT_BASE@l

// base address of SWT module

e_li

r0, SWT_UNLOCK_KEY1

e_stw

r0, SWT_REG_SR (r7)

// 1. key

e_li

r0, SWT_UNLOCK_KEY2

e_stw

r0, SWT_REG_SR (r7)

// 2. key -> soft lock disabled

e_lwz

r0, SWT_REG_CR (r7)

// read CR register

se_bclri r0, 31

// clear WEN bit (disable WEN)

e_stw

r0, SWT_REG_CR (r7)

// write modified value back

A.13

Init whole RAM

e_lis

r3,__wrs_ramsize_words@h

// size of ECC prot. SRAM in words

e_or2i

r3,__wrs_ramsize_words@l

// = size in bytes /4

mtctr

// copy this value to counter gpr

e_lis

r7,__wrs_ramstart@h

// r7 is now our ram pointer

e_or2i

r7,__wrs_ramstart@l

// initialized to start of SRAM

se_subi

r7,0x04

// and now to 1 word location less

e_lis

r3,ECC_RAM_INIT_VALUE@h

e_or2i

r3,ECC_RAM_INIT_VALUE@l

sram_loop:

e_stwu

r3,0x04(r7)

// write r3, to r7+4 and update r7

e_bdnz

sram_loop

// decr. counter gpr,loop if not 0

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