AN4253 datasheet(34/44 Pages) STMICROELECTRONICS

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asm examples

AN4253

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DocID024255 Rev 2

#define

ME_GS_MODE_DRUN

// current mode DRUN

#define

ME_GS_MTRANS

// position of bit for e_btsti instr.

#define

ME_GS_SYSCLK_MASK 0x000F

// mask of system clk field

#define

ME_MCTL_DRUN_R1

0x30005AF0 // 1.step in mode transition request

#define

ME_MCTL_DRUN_R2

0x3000A50F // 2.step in mode transition request

#define

ME_MC_XOSCON

// bit position for se_bseti instr.

#define

ME_MC_PLL0ON

// bit position for se_bseti instr.

#define

ME_MC_SYSCLK_PLL

0x0004

// value for e_or2i instr.

#define

ME_RUNPC_DRUN

// bit position for se_bseti instr.

#define

ME_PCTL_RUNPC1

// pointer to RUN_PC1 configuration

// AIPS peripheral bridge

#define

AIPS_BASE

0xFFF00000 // peripheral bridge base address

#define

AIPS_REG_MPROT

0x0000

// register offset from AIPS_BASE

#define

AIPS_MPROT_ENABLE 0x77770070 // Core0,1, DMA0, FlexRay as superuser

// Core Cache memory

#define

CACHE_REG_L1CSR1

1011

// SPR register number

#define

CACHE_ICE_BIT

0x0001 // for e_li instruction

// CGM block

#define

CGM_BASE

0xC3FE0000 // base address of CGM module

#define

CGM_REG_AC3SC

0x0398

// register offset from CGM_BASE

#define

CGM_AC3SC_XOSC 0x0100

// value for PLL input AUX3 bridge

// XOSC block (CGM base)

#define

XOSC_REG_OSCCTL 0x0000

// register offset from CGM_BASE

#define

XOSC_EOCV_IMASK 0xFF00

// mask to clear EOCV default value

#define

XOSC_EOCV_VALUE 0x009C

// cca 2ms for 40MHz crystal

// FMPLL0 block (CGM base)

#define

FMPLL0_REG_CR 0x00A0

// register offset from CGM_BASE

#define

FMPLL0_SLOCK

// bit position for e_btsti instr.

#define

FMPLL0_IDF

0x0C00

// 3 = divide by 4

#define

FMPLL0_ODF

0x0100

// 1 = divide by 4

#define

FMPLL0_NDIV

0x0030

// 48 = multiply by 48

#define

FMPLL0_VALUE

(FMPLL0_IDF | FMPLL0_ODF | FMPLL0_NDIV)

A.2

Core register init (LSM)

// selected core SPRs

mtcrf 0xFF,r31 // Condition register

mtspr 285,r31 // TBU

mtspr 284,r31 // TBL

mtspr 272,r31 // SPRG0

mtspr 273,r31 // SPRG1

mtspr 274,r31 // SPRG2

mtspr 275,r31 // SPRG3

mtspr 276,r31 // SPRG4

mtspr 277,r31 // SPRG5

mtspr 278,r31 // SPRG6

mtspr 279,r31 // SPRG7

mtspr 604,r31 // SPRG8

mtspr 605,r31 // SPRG9

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