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AN4253

asm examples

Appendix A

asm examples

All ‘asm’ examples here are built with WindRiver compiler toll with preprocessing on

assembly files set on. Preprocessor directives are used to make the code more readable.

Readable code is prioritized to time or space optimization.

A.1

Symbol defines

// MSR value to set after the reset

#define

STARTUP_MSR 0x21200 // CE|ME|DE

// Software watchdog module

#define

SWT_BASE

0xFFF38000 // Software watchdog base address

#define

SWT_REG_CR

0x0000

// registers offset

#define

SWT_REG_SR

0x0010

#define

SWT_UNLOCK_KEY1 0xC520

// key1 for soft_lock unlock

#define

SWT_UNLOCK_KEY2 0xD928

// key2 for soft_lock unlock

// FLASH registers

#define

FLASH_BASE

0xC3F88000 // Flash registers base address

#define

FLASH_REG_MCR

0x0000

// registers offset

#define

FLASH_EER_MASK 0x00008000 // EER bit

// FCCU module constants

#define

FCCU_BASE

0xFFE6C000 // FCCU module base address

#define

FCCU_REG_CTRL

0x0000

// registers offset

#define

FCCU_REG_CF

0x006C

#define

FCCU_REG_CFK

0x007C

#define

FCCU_REG_NCF

0x0080

#define

FCCU_REG_NCFK

0x0090

#define

FCCU_REG_STATUS

0x00C0

#define

FCCU_REG_IRQ

0x00E0

#define

FCCU_OPR_STATUS

0x3

// command to read Status

#define

FCCU_OPR_CF_READ

0x9

// command to read CF

#define

FCCU_OPR_NCF_READ 0xA

// command to read NCF

#define

FCCU_CFK_KEY

0x618B7A50 // key for CF faults clear operation

#define

FCCU_NCFK_KEY

0xAB3498FE // key for NCF faults clear operation

#define

FCCU_OPS_SUCCESS

// command successful status to wait for

#define

FCCU_CF_STCU

0x0850

// upper half word for compare instruction

#define

FCCU_NCF12

// BSTI instr has inverse bit numbering

// RGM module constants

#define

RGM_BASE

0xC3FE4000 // Reset module base address

#define

RGM_REG_FESDES

0x0000

// register offset from RGM_BASE

#define

RGM_DES_MASK

0x8000FFFF // Destructive resets status bit mask

// MODE ENTRY module constants

#define

ME_BASE

0xC3FDC000 // Mode Entry base address

#define

ME_REG_GS

0x0000

// register offsets from ME_BASE

#define

ME_REG_MCTL

0x0004

#define

ME_REG_DRUN_MC

0x002C

#define

ME_REG_RUN_PC1

0x0084

#define

ME_REG_PCTL_CRC 0x00FA

#define

ME_GS_MODE_SAFE 2

// current mode SAFE

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