 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
AN4253 датащи(PDF) 40 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
AN4253 датащи(HTML) 40 Page - STMicroelectronics |
|
|
40 / 44 page  asm examples AN4253 40/44 DocID024255 Rev 2 e_stw r0, ME_REG_MCTL (r7) // 2. step - inverted key // wait for transition to complete (test of GS.MTRANS bit) me_wait_xoscon: e_lwz r0, ME_REG_GS (r7) // read GS register se_btsti r0, ME_GS_MTRANS // test the MTRANS bit se_bc 0,2,me_wait_xoscon // if '1' > wait in loop // select XOSC as input to FMPLL0 block e_li r0, CGM_AC3SC_XOSC // prepare value e_sth r0, CGM_REG_AC3SC (r6) // write it to CGM_AC3SC register // configure FMPLL0 e_li r0, FMPLL0_VALUE // prepare value for FMPPL0 configuration e_sth r0, FMPLL0_REG_CR (r6) // write it to FMPLL0_CR register // enable FMPLL0 in DRUN mode e_lwz r0, ME_REG_DRUN_MC (r7) // read actual value of ME_DRUN_MC reg. se_bseti r0, ME_MC_PLL0ON // set bit PLL0ON e_stw r0, ME_REG_DRUN_MC (r7) // update ME_DRUN_MC register // mode transition -> DRUN e_lis r0, ME_MCTL_DRUN_R1@h e_or2i r0, ME_MCTL_DRUN_R1@l e_stw r0, ME_REG_MCTL (r7) // 1. step - normal key e_lis r0, ME_MCTL_DRUN_R2@h e_or2i r0, ME_MCTL_DRUN_R2@l e_stw r0, ME_REG_MCTL (r7) // 2. step - inverted key // wait for transition to complete (test of GS.MTRANS bit) me_wait_pll0on: e_lwz r0, ME_REG_GS (r7) // read GS register se_btsti r0, ME_GS_MTRANS // test the MTRANS bit se_bc 0,2,me_wait_pll0on // if '1' > wait in loop // wait for PLL lock event pll_wait_lock: e_lwz r0, FMPLL0_REG_CR (r6) // read FMPLL0.CR register se_btsti r0, FMPLL0_SLOCK // test LOCK bit se_bc 1,2,pll_wait_lock // if '0' > wait in loop // enable peripherals needed in next startup steps e_lwz r0, ME_REG_RUN_PC1 (r7) // read value of ME_RUN_PC1 register se_bseti r0, ME_RUNPC_DRUN // set DRUN bit e_stw r0, ME_REG_RUN_PC1 (r7) // write value back e_li r0, ME_PCTL_RUNPC1 // prepare value for PCTL e_stb r0, ME_REG_PCTL_CRC (r7) // set value to ME_PCTL_CRC register // select PLL for system clock e_lwz r0, ME_REG_DRUN_MC (r7) // read current value of ME_DRUN_MC reg e_or2i r0, ME_MC_SYSCLK_PLL // set PLL as system clock e_stw r0, ME_REG_DRUN_MC (r7) // write the value back // mode transition -> DRUN e_lis r0, ME_MCTL_DRUN_R1@h e_or2i r0, ME_MCTL_DRUN_R1@l e_stw r0, ME_REG_MCTL (r7) // 1. step - normal key |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
