28F020 datasheet(16/38 Pages) INTEL

16 / 38 page

28F020

3.0 DESIGN CONSIDERATIONS

3.1

Two-Line Output Control

Flash memories are often used in larger memory

arrays. Intel provides two read control inputs to

accommodate multiple memory connections. Two-

line control provides for:

the lowest possible memory power dissipation

and,

complete assurance that output bus contention

will not occur.

To efficiently use these two control inputs, an

address decoder output should drive chip enable,

while the system’s read signal controls all flash

memories

and other

parallel

memories.

This

assures that only enabled memory devices have

active outputs, while deselected devices maintain

the low power standby condition.

3.2

Power Supply Decoupling

Flash

memory

power-switching

characteristics

require

careful

device

decoupling.

System

designers are interested in three supply current

(ICC) issues—standby, active, and transient current

peaks produced by falling and rising edges of chip

enable. The capacitive and inductive loads on the

device outputs determine the magnitudes of these

peaks.

Two-line control and proper decoupling capacitor

selection will suppress transient voltage peaks.

Each device should have a 0.1 µF ceramic

capacitor connected between VCC and VSS, and

between VPP and VSS.

Place the high-frequency, low-inherent-inductance

capacitors as close as possible to the devices.

Also, for every eight devices, a 4.7 µF electrolytic

capacitor should be placed at the array’s power

supply connection, between VCC and VSS. The bulk

capacitor will overcome voltage slumps caused by

printed circuit board trace inductance, and will

supply charge to the smaller capacitors as needed.

3.3

VPP Trace on Printed Circuit

Boards

Programming flash memories, while they reside in

the target system, requires that the printed circuit

board designer pay attention to the VPP power

supply trace. The VPP pin supplies the memory cell

current for programming. Use similar trace widths

and layout considerations given the VCC power bus.

Adequate VPP supply traces and decoupling will

decrease VPP voltage spikes and overshoots.

3.4

Power-Up/Down Protection

The 28F020 is designed to offer protection against

accidental erasure or programming during power

transitions.

Upon

power-up,

the

28F020

indifferent as to which power supply, VPP or VCC,

powers up first. Power supply sequencing is not

required. Internal circuitry in the 28F020 ensures

that the command register is reset to the read

mode on power-up.

A system designer must guard against active

writes for VCC voltages above VLKO when VPP is

active. Since both WE# and CE# must be low for a

command write, driving either to VIH will inhibit

writes. The control register architecture provides an

added level of protection since alteration of

memory contents only occurs after successful

completion of the two-step command sequences.

3.5

28F020 Power Dissipation

When designing portable systems, designers must

consider battery power consumption not only during

device operation, but also for data retention during

system idle time. Flash nonvolatility increases the

usable battery life of your system because the

28F020 does not consume any power to retain

code or data when the system is off. Table 4

illustrates the power dissipated when updating the

28F020.

28F020 датащи(PDF) 16 Page - Intel Corporation

28F020 датащи(HTML) 16 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

датащи скачать

ссылки URL