E

28F020

9

Table 2. 28F020 Bus Operations

Mode

CE#

OE#

WE#

Read

Data Out

Output Disable

XX

Tri-State

READ-

Standby

XX

X

X

Tri-State

ONLY

Intelligent Identifier

Data = 89H

Intelligent Identifier

Data = BDH

Read

READ/

Output Disable

XX

Tri-State

WRITE

XX

X

X

Tri-State

Write

NOTES:

1.

Refer to

2.

Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. All other

addresses low.

3.

4.

5.

6.

Refer to Table 3 for valid data-in during a write operation.

7.

2.2

Write Protection

at high voltage. Depending upon the application,

power supply switchable—available only when

the contents of the register default to the Read

command,

making

the

28F020

a

read

only

memory. In this mode, the memory contents

cannot be altered.

Or, the system designer may choose to “hardwire”

available. In this case, all command register

Protection).

The

28F020

is

designed

to

accommodate

either

design

practice,

and

to

encourage optimization of the processor memory

interface.

The two step program/erase write sequence to the

command register provides additional software

write protection.

2.2.1

BUS OPERATIONS

2.2.1.1

Read

The 28F020 has two control functions, both of

which must be logically active, to obtain data at the

outputs. Chip Enable (CE#) is the power control

and should be used for device selection. Output

Enable (OE#) is the output control and should be

used

to

gate

data

from

the

output

pins,

independent of device selection. Refer to AC read

timing waveforms.

be used to access array data, to output the

intelligent identifier codes, and to access data for

the read operation can only access the array data.