28F016SA datasheet(5/55 Pages) INTEL

5 / 55 page

28F016SA

1.0

INTRODUCTION

The documentation of the Intel 28F016SA memory

device includes this datasheet, a detailed user’s

manual, and a number of application notes, all of

which are referenced at the end of this datasheet.

The datasheet is intended to give an overview of the

chip feature-set and of the operating AC/DC

specifications.

The 16-Mbit Flash Product Family

User’s Manual provides complete descriptions of

the user modes, system interface examples and

detailed descriptions of all principles of operation. It

also contains the full list of software algorithm

flowcharts, and a brief section on compatibility with

Intel 28F008SA.

1.1

Product Overview

The 28F016SA is a high-performance 16-Mbit

(16,777,216 bit) block erasable nonvolatile random

access memory organized as either 1 Mword x

16 or 2 Mbyte x 8. The 28F016SA includes thirty-

two 64-KB (65,536) blocks or thirty-two 32-KW

(32,768) blocks. A chip memory map is shown in

Figure 4.

The implementation of a new architecture, with

many enhanced features, will improve the device

operating characteristics and results in greater

product reliability and ease-of-use.

Among

the

significant

enhancements

the

28F016SA:

• 3.3V Low Power Capability

• Improved Program Performance

• Dedicated Block Program/Erase Protection

A 3/5# input pin reconfigures the device internally

for optimized 3.3V or 5.0V read/program operation.

The 28F016SA will be available in a 56-lead,

1.2 mm thick, 14 mm x 20 mm TSOP type I

package or a 56-lead, 1.8 mm thick, 16 mm x

23.7 mm SSOP package. The TSOP form factor

and pinout allow for very high board layout

densities. SSOP packaging provides relaxed lead

spacing dimensions.

A Command User Interface (CUI) serves as the

system interface between the microprocessor or

microcontroller and the internal memory operation.

Internal algorithm automation allows

word/byte

programs

and

block

erase

operations

executed using a two-write command sequence to

the CUI in the same way as the 28F008SA 8-Mbit

FlashFile memory.

A superset of commands have been added to the

basic 28F008SA command-set to achieve higher

program

performance

and

provide

additional

capabilities. These new commands and features

include:

• Page Buffer Writes to Flash

• Command Queueing Capability

• Automatic Data Programs during Erase

• Software Locking of Memory Blocks

• Two-Byte Successive Programs in 8-bit

Systems

• Erase All Unlocked Blocks

Writing of memory data is performed in either byte

or word increments typically within 6 µs, a 33%

improvement over the 28F008SA. A block erase

operation erases one of the 32 blocks in typically

0.6 sec, independent of the other blocks, which is a

65% improvement over the 28F008SA.

Each block can be written and erased a minimum of

100,000 cycles. Systems can achieve typically one-

million block erase cycles by providing wear-leveling

algorithms and graceful block retirement. These

techniques have already been employed in many

flash file systems. Additionally, wear leveling of

block erase cycles can be used to minimize the

program/erase

performance

differences

across

blocks.

The 28F016SA incorporates two Page Buffers of

256 bytes (128 words) each to allow page data

writes. This feature can improve a system write

performance by up to 4.8 times over previous flash

memory devices.

All operations are started by a sequence of

command writes to the device. Three Status

Registers (described in detail later) and a RY/BY#

output pin provide information on the progress of

the requested operation.

While the 28F008SA requires an operation to

complete

before

the

operation

can

requested, the 28F016SA allows queueing of the

next operation while the memory executes the

current operation. This eliminates system overhead

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