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28F016SA датащи(PDF) 41 Page - Intel Corporation

номер детали 28F016SA
подробное описание детали  28F016SA 16-MBIT (1 MBIT X 16, 2 MBIT X 8)FlashFile MEMORY
PDF  55 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

28F016SA датащи(HTML) 41 Page - Intel Corporation

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28F016SA
41
NOTES:
CE# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
1.
Read timings during data program and block erase are the same as for normal read.
2.
Refer to command definition tables for valid address and data values.
3.
Sampled, but not 100% tested.
4.
Data program/block erase durations are measured to valid Status Register data.
5.
Word/byte program operations are typically performed with 1 programming pulse.
6.
Address and data are latched on the rising edge of WE# for all command write operations.
7.
This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office
for more information.
V
V
WE# (W)
OE# (G)
RP# (P)
V
PP
CEx # (E)
(V)
DEEP
POWER-DOWN
IH
IL
V
V
IH
IL
V
V
IH
IL
ADDRESSES (A)
t
WHEH
ELWL
t
t
WHDX
WHWL
t
V
V
IH
IL
t
WLWH
t
DVWH
V
IH
IL
V
V
IH
V
IL
PHWL
t
HIGH Z
IN
DD
IN
IN
A
t
t
QVVL
D
IN
IL
V
PPH
V
IN
V
t
VPWH
READ EXTENDED
STATUS REGISTER DATA
DATA (D/Q)
WHQV1,2
WRITE DATA-WRITE OR
ERASE SETUP COMMAND
WRITE VALID ADDRESS
& DATA (DATA-WRITE) OR
ERASE CONFIRM COMMAND
AUTOMATED DATA-WRITE
OR ERASE DELAY
V
V
RY/BY# (R)
t
WHRL
t
WHGL
OH
OL
V
V
IH
IL
ADDRESSES (A)
t
AVAV
AVWH
t
t
WHAX
IN
A
READ COMPATIBLE
STATUS REGISTER DATA
D
IN
WRITE READ EXTENDED
REGISTER COMMAND
A=RA
NOTE 1
NOTE 2
NOTE 3
NOTE 4
D
OUT
t
RHPL
t
GHWL
NOTE 5
PPL
V
t
AVAV
AVWH
t
t
WHAX
0489_14
NOTES:
1.
This address string depicts data program/block erase cycles with corresponding verification via ESRD.
2.
This address string depicts data program/block erase cycles with corresponding verification via CSRD.
3.
This cycle is invalid when using CSRD for verification during data program/block erase operations.
4.
CEX# is defined as the latter of CE0# or CE1# going low or the first of CE0# or CE1# going high.
5.
RP# low transition is only to show tRHPL; not valid for above read and program cycles.
Figure 15. AC Waveforms for Command Write Operations



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