HDM8513 datasheet(48/67 Pages) HYNIX

48 / 67 page

Test Set-up

The eight bit data written to this location defines the data presented on

the 16 bit test bus. For configurations where the data is updated once

per symbol period, the data changes at the rising edge of

SYMBOL_CLOCK

(in the case that SYMBOL_CLOCK remains high for consecutive

CLOCK

cycles, the test port data will also change accordingly during the high

period of SYMBOL_CLOCK due to the arrival of another symbol).

Bits [2:0]. Test port configuration

00H Output is tristate.

01H Test bits [15:8] provide the I baseband filter output. Test bits [7:0]

provide the Q baseband filter output. This information is updated once

per symbol period.

02H Test bits [15:0] provide the sixteen most significant bits of the

demodulator carrier phase test bits. This information is updated once

per

symbol period.

03H Test bits [15:0] provide the sixteen most significant bits of the

demodulator symbol phase test bits. This information is updated once

per

symbol period.

04H Test bits [15:8] provide the Reed Solomon output data. Test bits

[7:0] provide the deinterleaver output data. This information is updated at

the Reed Solomon clock rate; when the transport stream output is

configured to parallel output mode, DATA_CLK may be used as an

output clock for this data.

05H Test bits [15:10] provide the six bit narrowband AGC accumulator

value. Test bits [9:6] provide the four bit value of symbol phase. Test

bits [5:4] provide the two bit symbol count value. This information is

updated once per symbol period.

06H Test bits [13:8] provide the six bit I-channel data from the ADC.

Test bits [5:0] provides the six bit Q-channel data from the ADC. This

information is updated at the fixed rate sample clock.

07H In this mode the test pins are used as input pins. The internal

ADC is disabled, and the inputs at the test pins are fed directly to the

demodulator. Test bits [13:8] are used as I-channel input and test bits

[5:0] are used as Q-channel input. This information is updated at the

fixed rate sample clock.

Bit 3. Transport error Indicator Enable/Disable

Enables/Disables the transport error indicator,1 bit indicator in transport

header. When this bit is set to 1 and if transport error is internally

detected the transport error indicator bit is set to 1. When zero this

functionality is disabled.

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