HDM8513 datasheet(37/67 Pages) HYNIX

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DATA_CLK

The DATA_CLK is used to latch data and control signal of transport

stream. The data and control signals can be programmed to be

latched either at positive or negative edge of DATA_CLK. This signal is

used in conjunction with DATA_VALID to transfer data from the

HDM8513A. The DATA_CLK will continue to toggle during the 16

bytes that the DATA_VALID signal indicates that no data is available

(see figure 9 and 10).

DATA_VALID

When this signal is true, data is valid. This signal is not true during

the time the 16 bytes of redundancy information is transmitted for the

Reed Solomon decoder.

FRAME_SYNC

This signal is true at the first byte of a block of 188/144 bytes.

DATA_STB

This signal is used to transfer data from the HDM8513A to an MPEG

decoder. This signal goes from low to high when a new byte of a 188

/144byte MPEG2 data stream block is available. This signal is

inactive during the time the 16 redundancy bytes are transferred.

FRAME_ERROR

This signal goes true when the Reed Solomon decoder detects that an

uncorrectable number of errors have occurred. The error flag in the

MPEG2 output stream is also set when this flag goes high.

WB_AGC

This one bit output provides a measure of the external analog gain

required for optimizing the signal applied to the analog to digital

converters. This signal must be filtered, then applied to the analog

gain control.

CLOCK

This is a buffered clock output signal which may be used to drive other

devices with the same clock which drives the HDM8513A.

QPSK_LOCK

This signal goes true when the QPSK demodulator has achieved

phase lock.

VB_NODESYNC

This signal goes true when the Viterbi decoder has achieved node

synchronization.

LOCK

This signal goes true when the output data is valid and all

synchronization functions have been performed.

SYMBOL_CLOCK

This signal, used for test purposes, goes true for a duration of one

clock cycle for each received symbol. For symbol rates equal or

greater than half the clock frequency, this signal at times may remain

high for two successive clock cycles to indicate that two symbols have

occurred.

VB_DATA

The serial output of the Viterbi Decoder is provided on this pin. The

information rate at this point is less than the rate of the input clock

( less than 60Mbps if a 60MHz clock is employed). As long as valid

convolutional encoding is employed, there is no constraint that the

input signal adheres to MPEG2 format. This data is tapped priod to

the polarity correction circuitry, so the data at this point may be

inverted.

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