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HDM8513 датащи(PDF) 18 Page - Hynix Semiconductor |
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HDM8513 датащи(HTML) 18 Page - Hynix Semiconductor |
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18 / 67 page ![]() 18 3. Technical Overview 3.1 Dual Channel Analog to Digital Converter The block diagram shown below illustrates internal configuration of the Dual Channel ADC. Baseband signals, in-phase(I) and quadrature phase(Q), which are generated by down converters, are applied to the dual channel ADC and quantized to 6-bit digital codes respectively. The ADC is optimized to allow AC coupled inputs with full scale input range of 1V + or - 10%. An LSB weight is approximately 15.6 mV. The full scale input analog conversion range (Vpp) is determined by the voltages of VTOP and VBOT and simply equal to (VTOP - VBOT). The full scale range is defined as the voltage range that accommodates 63 codes of equally spaced LSBs. Also the ADC supplies its own reference voltages for A/D conversions. The voltages can be monitored by external reference pins. The VTOP, VBOT represent top and bottom reference voltages respectively. REF_I, REF_Q represent middle reference voltages for each channel. All these 4 reference voltage pins should be by-passed to GND via 0.1uF capacitors. The values of internally generated voltage of VTOP and VBOT are 2.0V and 1.0V respectively. Vpp can be adjusted by externally applying voltages to both VTOP and VBOT pins respectively when different conversion ranges are necessary. VTOP can be adjusted as high as 2.3V and VBOT can be as low as 0.5V. A larger input range can be established by taking VTOP higher and VBOT lower than on-chip generated voltages. To supply necessary bias voltages for AC coupled applications, REF_I and REF_Q, which are middle reference voltages for I and Q channel, are connected to the analog input pins (AIN_I and AIN_Q ) respectively through 40 kohm resistors, as shown in the block diagram. For DC coupled applications, these voltages can be used to feed back offset compensation signals. To insure optimum performance, a low impedance analog ground plane is recommended and should be separated from other digital ground planes. The analog power supplies should be by - passed at device to analog ground through 0.1uF ceramic capacitors. |
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