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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HDM8513 датащи(PDF) 26 Page - Hynix Semiconductor |
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HDM8513 датащи(HTML) 26 Page - Hynix Semiconductor |
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26 / 67 page  26 The table below illustrates a typical acquisition timing. For this example, the symbol rate is one half of the clock rate. The code rate is set to 5/6, which requires 13 trial and errors before node sync is achieved. The carrier search logic requires 10 dwells at different frequencies (500 symbols per dwell) before demodulator lock is achieved. Table 12: Example of Acquisition Timing Bit Times Symbols Clock Cycles Carrier Search 8,333 5,000 10,000 Viterbi Node Sync 2,652 1,591 3,182 Byte Sync 16,000 9,600 19,200 Deinterleaver Flush 19,584 11,750 23,500 Reed Solomon 1,632 979 1,958 Total Timing 48,201 26,950 57,840 The total time required for acquisition could vary widely, depending upon the carrier search range and the time required for Viterbi node sync. For this example, however, the Byte Sync time and the time required to flush the deinterleaver dominates the total time. If a 60MHz clock were employed, the total acquisition time would be 0.963 milliseconds for this example |
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