HDM8513 datasheet(24/67 Pages) HYNIX

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3.4 Viterbi Decoder

The Viterbi decoder accepts 3 bit soft decision samples of the in-phase (I) and quadrature (Q)

components of the received signal. Once QPSK lock has been achieved, the decoder searches for

the correct code rate, starting with rate 3/4, then proceeding to rate 2/3, 5/6, 7/8 and finally rate

1/2. Each of the possible synchronization phases at each rate is tested as well as the two

possible carrier phase ambiguity conditions. Polarity reversal is corrected in the word

synchronization logic. Viterbi lock is achieved when the trellis traceback algorithm converges, on

the average, within a prescribed number of symbols.

Although the algorithm automatically tests for carrier phase ambiguity, there is no provision to

automatically correct for phase reversal. Phase reversal can occur if the receiver chain, consisting

of an LNB and the tuner, provides an odd number of high side frequency translation operations. A

system may be required to operate with different LNBs, some of which provide phase reversal.

This condition may be corrected by the host processor, which can set a bit in the down converter

to correct for phase reversal.

The Viterbi decoder employs the radix two algorithm. The output buffer reserializes the data which

is made available, along with the Viterbi data clock as external signals. These signals permit

verification of the DVB specification which is referenced to the Viterbi decoder output.

ACS Array

Trace-back

RAM

Traceback Memory

Controller

Decoder

Quality

Estimate

Last-In

First-Out

Buffer

Data

Out

Viterbi

Lock

Clock

Out

Depuncturing

Logic

Branch Metric

Calculator

Change Puncture Phase

Change Carrier Phase

128

FIGURE 18: VITERBI DECODER

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