HT9480 datasheet(33/57 Pages) HOLTEK

33 / 57 page

User address format

A user address in the POCSAG code consists of

21 bits. Three of the 21 bits are coded in the

frame number and are therefore not explicitly

transmitted. In the decoder, the addresses A, B,

C, D, E and F can use 6 different frames respec-

tively. Every address has to be explicitly en-

abled by resetting the associated enable bit.

Examples:

Address decimal value: RICA=10535

Binary equivalent(14 bits): 10100100100111

Binary equivalent(18+3 bits):

000000010100100100111

A00 A01 A02 A03 A04 A05 A06 A07 A08

A09 A10 A11 A12 A13 A14 A15 A16 A17

FR12

FR11 FR10

Configuration

The program mode changes to the STANDBY

state by setting the ON bit high at any time. The

configuration RAM can be programmed only

when the value of the STB flag is 1. After the

configuration RAM is programmed and the ON

bit is set low, the system quits the program

mode and resumes normal operation.

Test mode

The test mode of the decoder is selected by

setting the TS pin low at any time. In the test

mode, the RF control outputs BS1 and BS3 are

set high constantly, but BS2 is set low.

After the TS pin is set high the decoder exits the

test mode.

RF control

The HT9480 provides the BS1-BS3 signals for

RF control.

• BS1: Receiver enabled

Receiver establishment

time (tBS1)

Option

512 bps

1200/2400 bps

SPF00 SPF01

7.81ms

53.33ms

15.63ms

6.67ms

31.25ms

13.33ms

62.50ms

26.67ms

• BS2: Quick charge

RF dc level adjustment

time (tBS2)

Option

512 bps

1200/2400 bps

SPF02 SPF03

7.81ms

1.67ms

11.71ms

6.67ms

15.63ms

11.67ms

19.53ms

13.33ms

• BS3: PLL enabled

PLL establishment

time (tBS3)

Option

512 bps

1200/2400 bps

SPF04 SPF05

0ms

31.25ms

26.67ms

46.87ms

40.00ms

62.50ms

53.33ms

Timing

HT9480

23th Feb ’98

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