HT9480 datasheet(9/57 Pages) HOLTEK

9 / 57 page

ister) (08H). Only the destination of the low-

order byte in the table is well-defined, the

other bits of the table word are all transferred

to the low portion of TBLH. TBLH is read only

while the table pointer (TBLP) is a read-

able/writable register (07H) used to indicate

the table location. Before accessing the table,

the location should be placed in TBLP. All of

the table related instructions require 2 cycles

to complete the operation. This feature is effi-

cient only for the movement of the blocks,

which may function as look-up tables or as a

normal program memory depending upon the

requirements.

Stack register – STACK

The stack register is a special memory port used

to save the contents of the PC. It is divided into

8 levels. The stack register is neither part of the

data nor part of the program, and is neither

readable nor writable. The activated level of the

stack register is indexed by the stack pointer

(SP), and is neither readable nor writable. At

the commencement of a subroutine call or an

interrupt acknowledge, the contents of the PC is

pushed onto the stack. At the end of the subrou-

tine or the interrupt routine, as signaled by a

return instruction (RET or RETI), the content s

of the PC is restored to its previous value from

the stack. After a chip reset, the SP will point to

the top of the stack.

If the stack is full and a non-masked interrupt

occurs, the interrupt request flag is recorded

but acknowledging is inhibited until the value

of the SP is decremented (by RET or RETI),

allowing that interrupt to be serviced. As this

feature can prevent a stack overflow, the use of

the structure becomes much easier. In a similar

case, if the stack is full, and a “CALL” is sub-

sequently executed, a stack overflow occurs and

the first entry is lost (only the most recent eight

return addresses are stored).

Data memory – RAM

The data memory (RAM) is designed in three

banks, i.e., bank 0, bank 1, and bank 27, and

comprised of four functional groups, namely

special function registers (of 22

×8 bits; 1×4 bit;

×2 bit in bank0), data memory (of 416×8 bits;

224

×8 in bank 0; 192×8 in bank 1), LCD display

mapping memory (of 35

×4 bits), and decoder

configuration RAM mapping memory (of 21

×8

bits). Most of the these groups are readable/wri-

table but some are read only.

Of the four functional groups, the special func-

tion registers of bank 0 consist of an indirect

addressing registers (IAR0;00H, IAR1;02H),

m em ory

po inter

re gisters

(MP0;01H,

MP1;03H), a memory bank pointer register

(BP;04H), an accumulator (ACC;05H), a pro-

gram counter low byte register (PCL;06H), a

table pointer (TBLP;07H), a table high-order

part register (TBLH;08H), a watchdog timer

option setting register (WDTS;09H), a status

counter (TMR0;0DH), a programmable timer

counter control register (TMRC0;0EH), a

timer/event counter (TMR1;10H), a timer/event

counter control register (TMRC1;11H), an input

port, two I/O ports (PA;12H, PB;14H, PC;16H),

two I/O control register (PBC;15H, PCC;17H), a

tone control register (1DH), a pager control reg-

ister (1EH), and a pager data register (1FH).

The special function registers are located from

00H to 1FH whereas the 32 global data regis-

Instruction(s)

Table Location

*12

*11

*10

*9*8*7*6*5*4*3*2*1*0

TABRDC [m]

P12

P11

P10

TABRDL [m]

11111

Notes:

*12~*0: Table location bits

@7~@0: Table pointer bits

P12~P8: Current program counter bits

HT9480

23th Feb ’98

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