HT9480 datasheet(12/57 Pages) HOLTEK

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Bits

Function

C is set if the operation results in a carry out in addition or if a borrow does not

take place in subtraction; otherwise C is cleared. C is also affected by a rotate

through carry instructions.

AC is set if the operation results in a carry out of the low nibbles in addition or if

a borrow from the high nibble into the low nibble does not take place in

subtraction; otherwise AC is cleared.

Z is set if the result of an arithmetic or a logic operation is zero; otherwise Z is

cleared.

OV is set if the operation results in a carry into the high-order bit but not a carry

out of the high-order bit, or vice versa; otherwise OV is cleared.

PD is cleared during power up, and set by a “HALT” instruction.

TO is cleared during power up or by a “CLR WDT” instruction and a “HALT”

instruction. TO is set by a current timer time-out.

−

Undefined, read as “0”

−

Undefined, read as “0”

STATUS register

Interrupts

The HT9480 provides an internal programma-

ble timer interrupt, an internal data ready in-

terrupt, timer/event counter interrupt, and a

battery fail interrupt. The internal data ready

interrupt and the battery fail interrupt employ

the same jump location (04H). The interrupt

control register (INTC;0BH) contains interrupt

control bits to set not only the enable/disable

status but also the interrupt request flags.

Once an interrupt subroutine is serviced, the

other interrupts will all be blocked (by clearing

the EMI bit). This scheme may prevent any

further interrupt nesting. Other interrupt re-

quests may occur during this interval, but only

the interrupt request flag is recorded. If a cer-

tain interrupt requires servicing within the

service routine, the EMI bit and the correspond-

ing bit of the INTC register may be set to permit

interrupt nesting. When the stack is full, the

interrupt request will not be acknowledged

even if the related interrupt is enabled, until

the SP is decremented. If immediate service is

desired, the stack should be prevented from

becoming full.

All of these interrupts can support the wake-up

function. As an interrupt is serviced, a control

transfer occurs by pushing the contents of the

PC onto the stack, followed by a branch to a

subroutine at the specified location in the pro-

gram memory. Only the contents of the PC is

pushed onto the stack. If the contents of the

altered by the interrupt service program which

corrupts the desired control sequence, the con-

tents should be saved in advance.

The data ready interrupt and battery fail inter-

rupt share the same subroutine call location

04H. Checking the battery fail interrupt bit

(BF;bit 4 of 1EH) and the data ready interrupt

bit (DR; bit 7 of 1EH) can determine which kind

of interrupt has occurred. The value of 1EH-bit

7 DR is cleared “0” by the decoder data ready

interrupt signal, and is set to “1” when the

µC

sets this bit high. Both interrupt bits are active

low.

The data ready interrupt is generated by the

pager decoder after a valid call is received, and

is initialized by setting the data ready interrupt

request flag (EIF; bit 4 of INTC) and the data

HT9480

23th Feb ’98

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