HT9480 datasheet(7/57 Pages) HOLTEK

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Execution flow

System Architecture

Execution flow

The HT9480 system clock can be derived from

either a crystal or an RC oscillator. It is inter-

nally divided into four non-overlapping clocks

denoted by P1, P2, P3, and P4. Each instruction

cycle consists of T1 to T4.

Instruction fetching and execution are pipe-

lined in such a way that a fetch takes an in-

struction cycle while decoding and execution

take the next instruction cycle. The pipelining

scheme causes each instruction to effectively

execute within a cycle. If an instruction changes

the content of the program counter two cycles

are required to complete the instruction.

Program counter – PC

The program counter (PC) is 13-bit wide and

controls the program ROM instruction se-

quence execution. The contents of the PC can

specify a of maximum 8192 addresses.

Mode

Program Counter

*12

*11

*10

Initial reset

000000000

Data ready interrupt and

battery fail interrupt

000000010

Programmable timer

interrupt

000000100

Timer/event Counter

interrupt

000000110

Skip

PC+2

Loading PCL

*12

*11

*10

Jump, call branch

#12

#11

#10

#9#8#7#6#5#4#3#2#1

Return from subroutine

S12

S11 S10

Program counter

Notes:

*12~*0: Program counter bits

#12~#0: Instruction code bits

S12~S0: Stack register bits

@7~@0: PCL bits

HT9480

23th Feb ’98

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