HT9480 datasheet(11/57 Pages) HOLTEK

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ters are from 20H to 3FH, where each bank

points to the same location. The other spaces,

namely 0CH, 0FH, 13H, the high nibble of 16H,

17H, and 18H~1CH, are all reserved for future

expansion usage; reading these locations will

get an “00H” value.

On the other hand, the general purpose data

memory, divided into three banks (bank 0, bank

1, and bank 27), is used for data, control infor-

mation, and LCD display control under instruc-

tion commands. The banks in the RAM are all

addressed from 40H to FFH, and are selected by

setting the value (“00H”: bank 0; “01H”: bank 1;

“1BH”: bank 27) of the bank pointer (BP;04H).

The bank27 memory is used for LCD display

mapping and the decoder configuration RAM

mapping. The spaces from 4FH to BFH and

from E3H to FFH, and the high nibble part from

C0H to E2H in bank 27 are all reserved for

future expansion usage; reading these locations

will derive “00H”.

The special registers, global data registers and

general data memory can directly perform

arithmetic, logic, increment, decrement, and ro-

tate operations. Each bit in the RAM can be set

and reset by “SET [m].i” and “CLR [m].i”, and

can also be indirectly accessible through the

memory pointer registers (MP0;01H, MP1;03H).

Of the special addresses, 1DH and 1FH cannot

directly do all these operations, because they

are not read and write accessible addresses.

1DH is a write-only address, 1FH a read-only

address, but these two addresses namely, 1DH

and 1FH can only perform operations by using

the “MOV” instruction.

Indirect addressing register

IARx (IAR0;00H, IAR1;02H) are indirect ad-

dress registers that are not physically imple-

mented. Any read/write operation of the IARx

accesses the data memory pointed to by MPx

(MP0;01H, MP1;03H). Reading the indirect ad-

dressing register itself will indirectly derive

00H, while writing the indirect addressing reg-

ister indirectly will lead to no operations. (IAR0,

MP0) is indirectly addressable in bank 0, but

(IAR1, MP1) is available for all banks.

Accumulator – ACC

The accumulator (ACC) relates to the ALU opera-

tions. It is also mapped to location 05H of the data

memory and is capable of carrying out immediate

data operations. Data movement between these

two data memories has to pass through the ACC.

Arithmetic and logic unit – ALU

This circuit performs 8-bit arithmetic and logic

operations, and provides the following functions:

• Arithmetic operation (ADD, ADC, SUB, SBC, DAA)

• Logic operation (AND, OR, XOR, CPL)

• Rotation (RL, RR, RLC, RRC)

• Increment and decrement (INC, DEC)

• Branch decision (SZ, SNZ, SIZ, SDZ, etc.)

The ALU not only saves the results of data

operation, but also changes the contents of the

status register.

Status register – STATUS

The status register (0AH) is 8-bit wide. It contains

a zero flag (Z), a carry flag (C), an auxiliary carry

flag (AC), an overflow flag (OV), a powerdown flag

(PD), and a WDT time-out flag (TO). The status

but also controls the operation sequence.

The status register, like most other registers,

can be altered by instructions except for the TO

and PD flags. Any data written into the status

noted that operations related to the status reg-

ister may derive different results from those

intended. For example, clearing the status reg-

ister CLR [0AH] has no effect on the TO and PD

flags, and the value of the zero flag is also “1”,

i.e., UU0100 is the data in the register, where

the value of U is an unchanged value.

The Z, OV, AC, and C flags generally reflect the

status of the latest operations.

On entering an interrupt sequence or executing

a subroutine call, the status register will not be

automatically pushed onto the stack. If the con-

tents of the status is important, and if the sub-

routine may corrupt the status register, the

programmer should take precautions to save it

properly.

HT9480

23th Feb ’98

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