LP55281TLSLASHNOPB datasheet(26/35 Pages) TI1

26 / 35 page

SDA

SCL

LP55281

SNVS458B – JUNE 2007 – REVISED JUNE 2007

www.ti.com

Figure 27. I2C Timing Diagram

Symbol

Parameter

Limit

Units

Min

Max

Hold Time (repeated)

0.6

µs

START condition

Clock Low Time

1.3

µs

Clock High Time

600

Setup Time for a Repeated

600

START Condition

Data Hold Time

Data Setup TIme

100

Rise Time of SDA and SCL

20 + 0.1Cb

300

Fall Time of SDA and SCL

15 + 0.1Cb

300

Set-up Time for STOP

600

condition

Bus Free Time between a

1.3

µs

STOP and a START

Condtion

Capacitive Load for Each

200

Bus Line

NOTE

Data guaranteed by design

Recommended External Components

OUTPUT CAPACITOR, COUT:

The output capacitor COUT directly affects the magnitude of the output ripple voltage. In general, the higher the

value of COUT, the lower the output ripple magnitude. Multilayer ceramic capacitors with low ESR are the best

choice. At the lighter loads, the low ESR ceramics offer a much lower VOUT ripple than the higher ESR tantalums

of the same value. At the higher loads, the ceramics offer a slightly lower VOUT ripple magnitude than the

tantalums of the same value. However, the dv/dt of the VOUT ripple with the ceramics is much lower than the

tantalums under all load conditions. Capacitor voltage rating must be sufficient, 10V or greater is recommended.

Some ceramic capacitors, espesically those in small packages, exhibit a strong capacitance reduction with the

increased applied voltage. The capacitance value can fall to below half of the nominal capacitance. Too low

output capacitance will increase the noise and it can make the boost converter unstable.

INPUT CAPACITOR, CIN:

The input capacitor CIN directly affects the magnitude of the input ripple voltage and to a lesser degree the VOUT

ripple. A higher value CIN will give a lower VIN ripple. Capacitor voltage rating must be sufficient, 10V or greater is

recommended.

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