start

msb Chip Address lsb

w

ack

msb Register Add lsb

ack

msb

DATA

lsb

ack

stop

ack from slave

ack from slave

ack from slave

SCL

SDA

start

id = 4Ch

w

ack

addr = 02H

ack

ack

address 02H data

stop

ack from slave

msb Chip Address lsb

ack from slave

w

msb Register Add lsb

rs

r

msb

DATA

lsb

stop

ack from slave

repeated start

data from slave

start

Id = 4Ch

w ack

addr = h00

ack

rs

r ack

Address 00h data

ack stop

msb Chip Address lsb

Id = 4Ch

start

SCL

SDA

ack/nack from

master

LP55281

www.ti.com

SNVS458B – JUNE 2007 – REVISED JUNE 2007

•

If the master device sends acknowledge signal, the control register address will be incremented by one. Slave

device sends data byte from addressed register.

•

Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop

condition.

Address Mode

Data Read

<Start Condition>

<Slave Address><r/w = 0>[Ack]

<Register Address>[Ack]

<Repeated Start Condition>

<Slave Address><r/w = 1>[Ack]

[Register Data]<Ack or NAck>

...additional reads from subsequent register address possible

<Stop Condition>

Data Write

<Start Condition>

<Slave Address><r/w = 0>[Ack]

<Register Address>[Ack]

<Register Data>[Ack]

...additional writes to subsequent register address possible

<Stop Condition>

< > Data from master, [ ] data from slave

Figure 25. Register Read Format

When a READ function is to be accomplished, a WRITE function must precede the READ function, as shown in

the Read Cycle waveform.

Figure 26. Register Write Format

•

w = write (SDA = 0)

•

r = read (SDA = 1)

•

ack = acknowledge (SDA pulled down by either master or slave)

•

rs = repeated start

•

id = 7-bit device address

Copyright © 2007, Texas Instruments Incorporated

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