SDA

SCL

S

P

STO

S

1

2

3...6

7

8

9

Start

Condition

Acknowledge Signal

from Receiver

Transmitter Stays off the

Bus During the

Acknowledge Clock

SCL

SDA

data

change

allowed

data

valid

data

change

allowed

data

valid

data

change

allowed

LP55281

www.ti.com

SNVS458B – JUNE 2007 – REVISED JUNE 2007

Figure 21. Data Validity

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a

Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit first. After each byte, an Acknowledge signal must follow. The following

sections provide further details of this process.

Figure 22. Acknowledge Signal

The Master device on the bus always generates the Start and Stop Conditions (control codes). After a Start

Condition is generated, the bus is considered busy and it retains this status until a certain time after a Stop

Condition is generated. A high-to-low transition of the data line (SDA), while the clock (SCL) is high, indicates a

Start Condition. A low-to-high transition of the SDA line, while the SCL is high, indicates a Stop Condition

Figure 23. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction.

This allows another device to be accessed or a register read cycle.

Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the ninth clock pulse of the byte transfer. The transmitter

releases the SDA line (permits it to go high) to allow the receiver to send the acknowledge signal. The receiver

must pull down the SDA line during the acknowledge clock pulse and ensure that SDA remains low during the

high period of the clock pulse, thus signaling the correct reception of the last data byte and its readiness to

receive the next byte.

Copyright © 2007, Texas Instruments Incorporated

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