SCK

Data

BIT 1

LSB IN

LSB OUT

BIT 1

MSB OUT

BIT 7

BIT 8

BIT 9

BIT 14

MSB IN

R/W

Address

2

1

4

5

7

6

3

11

9

10

8

SS

SO

SI

12

LP55281

SNVS458B – JUNE 2007 – REVISED JUNE 2007

www.ti.com

Figure 20. SPI Timing Diagram

SPI Timing Parameters

Symbol

Parameter

Limit

Units

Min

Max

1

Cycle Time

70

ns

2

Enable Lead Time

35

ns

3

Enable Lag Time

35

ns

4

Clock Low Time

35

ns

5

Clock High Time

35

ns

6

Data Setup Time

20

ns

7

Data Hold Time

0

ns

8

Data Acces Time

20

ns

9

Disble Time

10

ns

10

Data Valid

20

ns

11

Data Hold Time

0

ns

NOTE

Data guaranteed by design

Interface Bus Overview

the device. This protocol uses a two-wire interface for bidirectional communications between the IC's connected

to the bus. The two interface lines are the Serial Data Line (SDA) and the Serial Clock Line (SCL). These lines

should be connected to a positive supply, via a pull-up resistor and remain HIGH even when the bus is idle.

For every device on the bus is assigned a unique address and it acts as a Master or a Slave, depending on

make sure that the LP55281 does not disturb the SDA and SCL lines.

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock's high period, the data should remain stable. Any changes on the

SDA line during the high states of the SCL and in the middle of the transaction, aborts the current transaction.

New data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

22

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