CS4812 datasheet(25/36 Pages) CIRRUS

25 / 36 page

CS4812

DS291PP3

consists of a start condition followed by its slave

address byte with the Read/Write bit set to 0. The

host controller then initiates a read preamble. The

read preamble is identical to the write preamble ex-

cept for the state of the Read/Write bit. The host

controller then sends a MAP byte which contains

the address of the control register to be accessed.

After receiving the MAP byte, the CS4812 returns

the contents of this register to the host controller.

The host controller may continue reading registers

by sending additional MAP bytes or complete the

transaction by initiating a stop condition. Figure 24

shows the SPI mode slave read flow diagram initi-

ated by the host microcontroller. Figure 25 shows

the I2C slave mode read flow diagram incorporat-

ing the DSP REQ signal. REQ is used to notify the

host controller that a data byte from the DSP is

waiting to be read.

The behavior of the REQ signal is dependent on

when data is written to the SCP output register in

relation to SCL and bit 1 of the current byte being

transferred. There are three cases of REQ behavior:

1. The REQ line will be de-asserted immediately

following the rising edge of SCL on the D1 bit of

the current byte being transferred if there is no data

in the SCP output register. The REQ line remains

de-asserted and a stop condition should be issued

by the bus master, thus completing the transfer.

2. If data is written to the SCP output register prior

to the rising edge of SCL for the D1 bit, REQ will

remain asserted. The bus master should continue to

shift out this new byte.

3. If data is placed in the SCP output register by the

DSP after the rising edge of SCL for the D1 bit,

REQ will be immediately re-asserted, thus creating

a pulse on REQ. The byte in the SCP out register

may be read by the bus master as part of the current

transaction or may be read later as part of a new

read transaction.

The CS4812 has a MAP auto increment capability

which allows block reads or writes of successive

control port registers.This feature is enabled by set-

ting the INCR bit in the MAP byte.

During a write sequence, multiple bytes may be

written by continuing to send data bytes to the

CS4812 after the first data byte and before initiat-

ing a stop condition. If auto increment is disabled,

the last data byte sent will appear in the register

designated by the MAP. If auto increment is en-

SEND I2C START

WRITE ADDRESS BYTE

WITH R/W BIT = 0

GET ACK

READ DATABYTE

MORE BYTES

SEND ACK

SEND NACK

SEND I2C STOP

GET ACK

WRITE ADDRESS BYTE

WITH R/W BIT = 1

GET ACK

SEND I2C START

SEND MAP BYTE

Figure 24. I2C Slave Mode Read Flow Diagram

TO READ?

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