CS4812 datasheet(22/36 Pages) CIRRUS

22 / 36 page

CS4812

DS291PP3

should be issued by the bus master, thus complet-

ing the transfer.

2. If data is written to the serial control port output

data bit, REQ will remain asserted. The bus master

should continue to shift out this new byte.

3. If data is placed in the SCP output register by the

DSP after the rising edge of CCLK for the D2 bit,

REQ will be immediately re-asserted, thus creating

a pulse on REQ. The byte in the SCP out register

may be read by the bus master as part of the current

transaction or may be read later as part of a new

read transaction.

The CS4812 has a MAP auto increment capability

which allows block reads or writes of successive

control port registers.This feature is enabled by set-

ting the INCR bit in the MAP byte.

During a write sequence, multiple bytes may be

written by continuing to send data bytes to the

CS4812 after the first data byte and before de-as-

serting CS. If auto increment is disabled, the last

data byte sent will appear in the register designated

by the MAP. If auto increment is enabled, data

bytes sent following the first data byte will be writ-

ten to successive registers following that designat-

ed in the MAP.

SET CS LOW

WRITE ADDRESS BYTE

READ DATA BYTE

MORE BYTES

SET CS HIGH

WRITE ADDRESS BYTE

WRITE MAP BYTE

TOGGLE CS

WITH R/W BIT = 0

WITH R/W BIT = 1

Figure 18. SPI Slave Mode Read Flow Diagram

TO READ?

Figure 19. SPI Slave Mode Read from DSP Core

Flow Diagram using DSP REQ

SET CS LOW

WRITE ADDRESS BYTE

READ DATA BYTE

REQ STILL LOW?

SET CS HIGH

WRITE ADDRESS BYTE

WRITE MAP BYTE FOR

REQ LOW?

TOGGLE CS

WITH R/W BIT = 0

WITH R/W BIT = 1

DSP OUTPUT REGISTER

(MAP = 0X27)

FROM DSP OUTPUT REGISTER

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