CS4812

DS291PP3

9

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MASTER

Notes: 15. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after

RST is de-asserted and before the control port registers have been initialized.

16. Measured with a 2.2 k

Ω pull-up resistor to VD.

Parameter

Symbol

Min

Typ

Max

Units

SPI Master (AutoBoot) Mode (SPI/I2C = 0, SCPM/S = 1, Note 14)

CCLK Clock Frequency

(Note 15)

-Fs

-

kHz

CCLK Low Time

-1/(2*Fs)-

ns

CCLK High Time

-1/(2*Fs)-

ns

CCLK Rise Time

(Note 16)

-12

-

ns

CCLK Fall Time

(Note 16)

-12

-

ns

RST rising to CS falling

-42

-

µs

CS High Time Between Transmissions

37

-

-

µs

CS Falling to CCLK Edge

5-

-

µs

CS Falling to CDOUT valid

-

-

50

ns

CCLK Falling to CDOUT valid

--

100

ns

CDIN to CCLK Rising Setup Time

80

-

-

ns

CCLK Rising to DATA Hold Time

80

-

-

ns

CCLK Falling to CS rising

40

-

-

ns

t r2

t f2

t dsu t dh

t sch

t scl

CS

CCLK

CDIN

t css

t csh

t clcs

t srs

RST

t pd

CDOUT

t dv

Figure 2. SPI Control Port Master Mode (AutoBoot) Timing