CS4812

12

DS291PP3

Semiconductors.

22. Depending on the input clock configuration, CCLK may be up to 2*Fs temporarily during AutoBoot after

RST has been de-asserted and before the control port registers have been initialized.

23. Data must be held for sufficient time to bridge the worst case fall time of 300 ns for CCLK/SCL.

24. For both SDA transmitting and receiving.

Parameter

Symbol

Min

Typ

Max

Units

SCL Clock Frequency

(Note 22)

-Fs

-

kHz

Clock Low Time

-1/(2*Fs)

-

µs

Clock High Time

-1/(2*Fs)

-

µs

Bus Free Time Between Transmissions

4.7

-

-

µs

RST rising to start condition

-22

-

µs

Start Condition Hold Time

4.0

-

-

µs

Setup Time for Repeated Start Condition

13.5

-

-

µs

SDA Setup Time to SCL Rising

250

-

-

ns

SDA Hold Time from SCL Falling

(Note 23)

0-

-

µs

SCL falling to SDA Output Valid

--

1.5

µs

SCL and SDA Rise Time

(Note 24)

--

1

µs

SCL and SDA Fall Time

(Note 24)

--

300

ns

Setup Time for Stop Condition

4.7

-

-

µs

t

buf

t

hdst

t

hdst

t

low

t r

t f

t

hdd

t

high

t sud

tsust

t susp

Stop

Start

Start

Stop

Repeated

SDA

SCL

t

irs

RST

t

cldv

(output)