CS4812 datasheet(23/36 Pages) CIRRUS

23 / 36 page

CS4812

DS291PP3

During a read sequence, multiple bytes may be read

by continuing to clock out data bytes to the CS4812

after the first data byte and before de-asserting CS.

If auto increment is disabled, the last data byte read

will be the register designated by the MAP. If auto

increment is enabled, data bytes read following the

first data byte will be read from successive registers

following that designated in the MAP.

3.5.2

I2C Bus

The I2C bus interface implemented on the CS4812

consists of 3 digital signals, SCL, SDA and REQ.

SCL, or serial clock, is used to clock individual

data bits. SDA, or serial data, is a bidirectional data

line. REQ, the request pin, is used by the DSP to re-

quest a host read when operating in control port

slave mode. Two additional pins, AD1 and AD0,

are inputs which determine the 2 lowest order bits

of the 7-bit I2C device address.

SCL may be defined as an input or an output with

respect to the CS4812. If the serial control port of

the CS4812 is defined as the master, then SCL is an

open-drain output and requires a pull-up resistor as

shown in Figure 5. Conversely, if the serial control

port of the CS4812 is defined as the slave, then

SCL is an input.

SDA carries time-multiplexed bidirectional serial

data. It is open-drain and requires a pull-up resistor

as shown in Figure 5.

AD1 and AD0, the inputs which determine the 2

lowest order bits of the 8-bit I2C device address, are

meaningful only when the CS4812 is operating as

a slave device and may be tied to ground when the

CS4812 is configured for master mode.

When operating in control port slave mode, the

REQ output pin is used by the CS4812 DSP to re-

quest communication with the master.

3.5.2.1

I2C Master Mode

The I2C master mode is designed for read-only op-

eration during AutoBooting from a serial EE-

PROM. A typical AutoBoot sequence with a

Microchip X24256 serial EEPROM, or equivalent,

is shown in Figure 20. On exit from reset, the

CS4812 sends an initial write preamble to the EE-

PROM which consists of a I2C start condition and

the slave address byte. The slave address consists

of the 4 most significant bits set to 1010, the fol-

lowing 3 bits corresponding to the device select

bits, A2, A1 and A0 set to 000 and the last bit (R/W)

set to 0. Following this, a 2-byte EEPROM starting

address of 0x0000 is sent to the EEPROM. The 2-

byte EEPROM starting address uses only the low-

est 13 bits and sets the highest 3 bits to zero. To be-

gin reading from the EEPROM, the CS4812 sends

another start condition followed by a read pream-

ble. The read preamble is identical to the write pre-

amble except for the state of the R/W bit. The

CS4812 then automatically clocks out sequential

bytes from the EEPROM until the last byte has

been received. These bytes include initial values

for all control port registers as well as the DSP ap-

plication code. After the last byte, the CS4812 ini-

tiates a stop condition and begins program

execution. At this point, the serial control port be-

comes inactive until the next reset. Actual EE-

16 17 18 19

25 26 27 28 29

CHIP ADDRESS (WRITE)

CHIP ADDRESS (READ)

MEMORY ADDRESS

DATA

DATA +n

START

ACK

START

STOP

ACK

SCL

SDA

34 35 36 37

30 31 32 33

Figure 20. Control Port Timing, I2C Master Mode AutoBoot

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