CS4812 datasheet(20/36 Pages) CIRRUS

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CS4812

DS291PP3

a buffer may be required to minimize the capacitive

loading on CLKOUT.

CCLK and CS may be inputs or outputs with respect

to the CS4812. If the serial control port of the

CS4812 is defined as the master, then CCLK and CS

are outputs and CCLK requires a 2.2 k

Ω pull-up re-

sistor. If the CS4812 is defined as the slave, then

CCLK and CS are inputs and no pull-up resistor is re-

quired on CCLK.

3.5.1.1

SPI Master Mode

The SPI master mode is designed for read-only op-

eration during AutoBooting from a serial EE-

PROM. A typical AutoBoot sequence with a Xicor

X25650 serial EEPROM, or equivalent, is shown in

Figure 14. On exit from reset, the CS4812 asserts CS.

The 8-bit read instruction (00000011) is sent to the

EEPROM followed by a pre-defined 16-bit start ad-

dress.The CS4812 then automatically clocks out se-

quential bytes from the EEPROM until the last byte

has been received. After the last byte is received, the

CS4812 deasserts CS and begins program execution.

At this point, the serial control port becomes inactive

until the next reset.

3.5.1.2

SPI Slave Mode

In SPI slave mode, a write sequence from an exter-

nal host controller is shown in Figure 15. The host

controller asserts CS and sends a 16-bit write pre-

amble to the CS4812. This preamble consists of a

7-bit chip address (must be 0010000) followed by

a one-bit R/W (Read/Write) bit (set to 0 for write)

21 22 23 24

CDOUT

READ

COMMAND

16-BIT

ADDRESS = 0X0000

CDIN

DATA

MSB

1 0

0 0 0

1 1

CLK

9 10 11

30 31

25 26 27 28 29

DATA + n

1 0

Figure 14. Control Port Timing, SPI Master Mode AutoBoot

CDOUT

CLK

12 13 14 15

CDIN

CHIP ADDRESS (WRITE)

MAP BYTE

MSB

DATA

DATA +n

R/W

10 11

16 17 18 19 20 21 22

INCR

(input)

(output)

Figure 15. Control Port Timing, SPI Slave Mode Write

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