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CS4812 датащи(PDF) 7 Page - Cirrus Logic

номер детали CS4812
подробное описание детали  Fixed Function Multi-Effects Audio Processor
PDF  36 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4812 датащи(HTML) 7 Page - Cirrus Logic

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CS4812
DS291PP3
7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE
(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)
Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.
12. CDOUT should NOT be sampled during this time period.
13. DSPCLK frequency is twice the DSP instruction rate.
14. Timing is guaranteed by characterization. Production test guarantees functionality.
Parameter
Symbol
Min
Max
Unit
SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14)
CCLK Clock Frequency
fsck
-6
MHz
CCLK Low Time
tscl
66
-
ns
CCLK High Time
tsch
66
-
ns
Rise Time of Both CDIN and CCLK Lines
tr
-100
ns
Fall Time of Both CDIN and CCLK Lines
tf
-100
ns
Setup Time CDIN to CCLK Rising
tcdisu
40
-
ns
Hold Time CCLK Rising to CDIN
(Note 11)
tcdih
15
-
ns
Time from CCLK edge to CDOUT Valid
(Note 12)
tscdov
-45
ns
Rise Time for CDOUT
tcdor
-25
ns
Fall Time for CDOUT
tcdof
-25
ns
CS Falling to CCLK Rising
tcss
20
-
ns
Time from CCLK Falling to CS Rising
tsccsh
0-
ns
High Time Between Active CS
tcsht
1-
µs
Time from CCLK Rising to REQ Rising
(Note 13)
tscrh
-2*DSPCLK+10
ns
Rise Time for REQ
trr
-100
ns
Fall Time for REQ
trf
-100
ns



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