AT25DF161_13 datasheet(41/52 Pages) ETC2

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AT25DF161

Figure 13-1. RapidS Operation

14.

System Considerations

In an effort to continue our goal of maintaining world-class quality leadership, Adesto has been performing extensive

testing on the AT25DF161 that would not normally be done with a Serial Flash device. The testing that has been

performed on the AT25DF161 involved extensive, non-stop reading of the memory array on pre-conditioned devices. The

pre-conditioning of the devices, which entailed erasing and programming the entire memory array 10,000 times, was

done to simulate a customer environment and to exercise the memory cells to a certain degree.

The non-stop reading of the devices was done in three levels of granularity, with the first level involving a continuous,

looped read of 256-bytes (a single page) of memory, the second level involving a continuous, looped-read of a 4-Kbyte

(16 pages) portion of memory, and the third level entailing non-stop reading of the entire memory array. Read operations

were performed at both +25°C and +125°C and with a supply voltage of 3.7V, which exceeds the specified datasheet

operating voltage range.

The results of all of the extensive tests indicate that the contents of a portion of memory being read continuously could be

altered after 800,000,000 read operations only if that portion of the memory was not erased or reprogrammed at all

during the 800,000,000 read operations. If that portion of memory was reprogrammed at some point, then it would take

another 800,000,000 read operations after reprogramming before the contents could potentially be altered. For example,

if the Serial Flash is being used for boot code storage, then it would take 800,000,000 boot operations before that boot

code may become altered, provided that the boot code was not updated or reprogrammed. If an application was to read

the entire memory array non-stop at a clock frequency of 10MHz, it would take over 5 years to reach 800,000,000 read

operations.

Adesto firmly believes that this extended testing result should not be a cause for concern. We also believe that most, if not

all, applications will never read the same portion of memory 800,000,000 times throughout the life of the application

without ever updating that portion of memory.

MOSI

MISO

SCK

Slave CS

234567

BYTE A

MSB

LSB

BYTE B

MSB

LSB

MOSI = Master Out, Slave In

MISO = Master In, Slave Out

The Master is the ASIC/MCU and the Slave is the memory device.

The Master always clocks data out on the rising edge of SCK and always clocks data in on the falling edge of SCK.

The Slave always clocks data out on the falling edge of SCK and always clocks data in on the rising edge of SCK.

Master clocks out first bit of BYTE A on the rising edge of SCK

Slave clocks in first bit of BYTE A on the next rising edge of SCK

Master clocks out second bit of BYTE A on the same rising edge of SCK

Last bit of BYTE A is clocked out from the Master

Last bit of BYTE A is clocked into the slave

Slave clocks out first bit of BYTE B

Master clocks in first bit of BYTE B

Slave clocks out second bit of BYTE B

Master clocks in last bit of BYTE B

3687H–DFLASH–5/2013

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