AT25DF161_13 datasheet(39/52 Pages) ETC2

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AT25DF161

Figure 12-4. Resume from Deep Power-Down

12.5

Hold

The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock

sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program or

erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the erase

cycle will continue until it is finished.

The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the HOLD

pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be started

until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin and CS pin

are asserted.

While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be

ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.

To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If

the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK

low pulse.

If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be

aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.

SCK

ICC

3687H–DFLASH–5/2013

AT25DF161 датащи(PDF) 39 Page - List of Unclassifed Manufacturers