AT25DF161_13 datasheet(11/52 Pages) ETC2

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AT25DF161

the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will be

reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete

byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be

programmed is protected or locked down.

While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster

throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the

data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status

The device also incorporates an intelligent programming algorithm that can detect when a byte location fails to program

properly. If a programming error arises, it will be indicated by the EPE bit in the Status Register.

Figure 8-1.

Byte Program

Figure 8-2.

Page Program

8.2

Dual-Input Byte/Page Program

The Dual-Input Byte/Page Program command is similar to the standard Byte/Page Program command and can be used to

program anywhere from a single byte of data up to 256-bytes of data into previously erased memory locations. Unlike the

standard Byte/Page Program command, however, the Dual-Input Byte/Page Program command allows two bits of data to

be clocked into the device on every clock cycle rather than just one.

Before the Dual-Input Byte/Page Program command can be started, the Write Enable command must have been

previously issued to the device (see “Write Enable” on page 18) to set the Write Enable Latch (WEL) bit of the Status

SCK

3687H–DFLASH–5/2013

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