AT25DF161_13 datasheet(29/52 Pages) ETC2

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AT25DF161

The Program OTP Security Register command utilizes the internal 256-buffer for processing. Therefore, the contents of

the buffer will be altered from its previous state when this command is issued.

Figure 10-4. Program OTP Security Register

10.5

Read OTP Security Register

The OTP Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum

clock frequency specified by fMAX. To read the OTP Security Register, the CS pin must first be asserted and the opcode of

77h must be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to

specify the starting address location of the first byte to read within the OTP Security Register. Following the three address

bytes, two dummy bytes must be clocked into the device before data can be output.

After the three address bytes and the dummy bytes have been clocked in, additional clock cycles will result in OTP Security

device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping

around from the end of the register to the beginning of the register.

Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can

be deasserted at any time and does not require that a full byte of data be read.

Figure 10-5. Read OTP Security Register

SCK

3687H–DFLASH–5/2013

AT25DF161 датащи(PDF) 29 Page - List of Unclassifed Manufacturers