AT25DF161_13 datasheet(34/52 Pages) ETC2

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AT25DF161

the SPRL bit will not change, no potential Global Protect or Unprotect will be performed, and the WEL bit in the Status

If the WP pin is asserted, then the SPRL bit can only be set to a logical “1”. If an attempt is made to reset the SPRL bit to

a logical “0” while the WP pin is asserted, then the Write Status Register Byte 1 command will be ignored, and the WEL

bit in the Status Register will be reset back to the logical “0” state. In order to reset the SPRL bit to a logical “0”, the WP

pin must be deasserted.

Figure 11-2. Write Status Register Byte 1

11.3

Write Status Register Byte 2

The Write Status Register Byte 2 command is used to modify the RSTE and SLE bits of the Status Register. Using the Write

Status Register Byte 2 command is the only way to modify the RSTE and SLE bits in the Status Register during normal

device operation, and the SLE bit can only be modified if the sector lockdown state has not been frozen. Before the Write

Status Register Byte 2 command can be issued, the Write Enable command must have been previously issued to set the

WEL bit in the Status Register to a logical “1”.

To issue the Write Status Register Byte 2 command, the CS pin must first be asserted and the opcode of 31h must be

clocked into the device followed by one byte of data. The one byte of data consists of three don’t care bits, the RSTE bit

value, the SLE bit value, and three additional don’t care bits (see Table 11-4). Any additional data bytes that are sent to

the device will be ignored. When the CS pin is deasserted, the RSTE and SLE bits in the Status Register will be modified,

and the WEL bit in the Status Register will be reset back to a logical “0”. The SLE bit will only be modified if the Freeze

Sector Lockdown State command has not been previously issued.

The complete one byte of data must be clocked into the device before the CS pin is deasserted, and the CS pin must be

deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation, the state of

the RSTE and SLE bits will not change, and the WEL bit in the Status Register will be reset back to the logical “0” state.

Table 11-3.

Write Status Register Byte 1 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPRL

Global Protect/Unprotect

SCK

Table 11-4.

Write Status Register Byte 2 Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RSTE

SLE

3687H–DFLASH–5/2013

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