AFE032 datasheet(47/77 Pages) TI1

номер детали	AFE032

подробное описание детали	Power-Line Communications Analog Front-End

PDF	77 Pages

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

Table 24. REG_AFE_STATUS Register (Address = 0Ah)

IFLAG_INT

TFLAG_INT

Reserved

DIG_ERR_INT

Reserved

LEGEND: R/W = read and write; R = read-only; R0 = read '0' (these bits reset to '0' after being read).

Bit 7

IFLAG_INT

This bit is set when the PA enters the current limit state for at least 16,384 DAC_CLK cycles. This interrupt is

cleared after being read.

0 = PA current limit not detected (default)

1 = PA current limit detected

Bit 6

TFLAG_INT

This bit is set when the PA enters the thermal limit state. This interrupt is cleared after being read.

0 = PA thermal limit not detected (default)

1 = PA thermal limit detected

Bit 5

Reserved

This bit is reserved.

Default = 0

Bit 4

DIG_ERR_INT

This bit is set when a digital error is detected. The REG_DIG_ERROR register must be read in order to clear this

interrupt.

0 = Digital errors not detected (default)

1 = Digital errors detected

Bits[3:0]

Reserved

These bits are reserved.

Default = not applicable

Table 25. RESERVED Registers (Address = 0Bh to 0Ch)

Reserved

LEGEND: R = read-only.

These registers are reserved.

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