AFE032 datasheet(35/77 Pages) TI1

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AFE032

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SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

Power Amplifier Enable and Disable Sequences

Whether immediately after the initialization sequence or when transitioning from receiver mode to transmitter

mode, one of the PA enable sequences described in this section must be used each time the device initiates a

signal transmission on the power line via the power amplifier. The specific enable sequence used depends on

whether the DAC block is enabled at least 300 µs prior to the start of the PA enable sequence or not.

PA Enable Sequence for a DAC Already Enabled Case

Use the following sequence if the DAC has been enabled for at least 300 µs.

•

Simultaneously set the PA IQ current control bits (bits 6 and 7) and the PA current limit bits (bits 4 and 5) of

the REG_PA_CURRENT_CFG register. The PA IQ current control bits must be set to '10' (that is, the 95 mA

option). The PA current limit bit settings depend on the application.

•

Enable the Filter bias enable bit (bit 5) of the REG_DAC/HPF/LPF/PA_CTL register.

•

Write '1' to the TX enable bit (bit 4), and '0' to the RX enable bit (bit 3) of the REG_RX/TX_CTL register.

•

Wait for 50 µs.

•

Write B4 (hex) to the REG_DAC/HPF/LPF/PA_CTRL register. (This setting enables the PA internal sub-

regulation circuitry, maintains the LPF and filter bias, and keeps the DAC enabled while leaving the HPF and

PA output stage disabled.)

•

Wait for 20 µs.

•

Write BC (hex) to the REG_DAC/HPF/LPF/PA_CTRL register. (This setting enables the PA output stage

while keeping the PA internal sub-regulation circuitry, LPF, filter bias, and DAC enabled. The HPF remains

disabled.)

•

Enable the ENPAIQN bit (bit 3) and the ENPAIQP bit (bit 2) of the REG_PA_CURRENT_CFG register.

•

Enable the ENPCOMP bit (bit 7) and ENNCOMP bit (bit 6) of the REG_RX/TX_CTL register.

•

Set the Tx PGA gain to the desired value.

•

Wait for at least 20 DAC_CLK cycles.

•

Configure the device in DAC mode by taking the DAC pin high.

•

Write the desired samples to the DAC following the procedure outlined in the DAC Mode section.

PA Enable Sequence Starting from a DAC in Disabled State Case

Use the following sequence if the DAC is disabled or if it is enabled for less than 300 µs prior to the start of the

PA enable sequence:

•

Simultaneously set the PA IQ current control bits (bits 6 and 7) and PA current limit bits (bits 4 and 5) of the

REG_PA_CURRENT_CFG register. The PA IQ current control bits must be set to '10' (that is, the 95 mA

option). The PA current limit bit settings depend on the application.

•

Enable the DAC by writing '1' to the DAC enable bit (bit 2) and the Filter bias enable bit (bit 5) of the

REG_DAC/HPF/LPF/PA_CTL register.

•

Write '1' to the TX enable bit (bit 4), and '0' to the RX enable bit (bit 3) of the REG_RX/TX_CTL register.

•

Wait for 300 µs.

•

Write B4 (hex) to the REG_DAC/HPF/LPF/PA_CTRL register. (This setting enables the PA internal sub-

regulation circuitry, maintains the LPF and filter bias, and keeps the DAC enabled while leaving the HPF and

PA output stage disabled.)

•

Wait for 20 µs.

•

Write BC (hex) to the REG_DAC/HPF/LPF/PA_CTRL register. (This setting enables the PA output stage

while keeping the PA internal sub-regulation circuitry, LPF, filter bias, and DAC enabled. The HPF remains

disabled.)

•

Enable the ENPAIQN bit (bit 3) and the ENPAIQP bit (bit 2) of the REG_PA_CURRENT_CFG register.

•

Enable the ENPCOMP bit (bit 7) and ENNCOMP bit (bit 6) of the REG_RX/TX_CTL register.

•

Set the Tx PGA gain to the desired value.

•

Wait for at least 20 DAC_CLK cycles.

•

Configure the device in DAC mode by taking the DAC pin high.

•

Write the desired samples to the DAC following the procedure outlined in the DAC Mode section.

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