AFE032 datasheet(44/77 Pages) TI1

номер детали	AFE032

подробное описание детали	Power-Line Communications Analog Front-End

PDF	77 Pages

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AFE032

SBOS669A – AUGUST 2013 – REVISED DECEMBER 2013

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Table 20. REG_RX/TX_CTL Register (Address = 06h)

ENPCOMP

ENNCOMP

Reserved

TX enable

RX enable

TX_PGA gain

R/W

LEGEND: R/W = read and write.

Bit 7

ENPCOMP

This bit enables the PA positive start control.

0 = Disabled (default)

1 = Enabled

Bit 6

ENNCOMP

This bit enables the PA negative start control.

0 = Disabled (default)

1 = Enabled

Bit 5

Reserved

This bit is reserved.

Default = 0

Bit 4

TX enable

This bit enables and disables TX_PGA and configures the programmable filter for either Tx or Rx mode.

0 = Tx path disabled (default)

1 = Tx path enabled

Bit 3

RX enable

This bit enables and disables RX_PGA1 and RX_PGA2. This bit can either be left enabled or disabled during Tx

mode.

0 = Rx disabled (default)

1 = Rx enabled

Bits[2:0]

TX_PGA gain

These bits select the TX_PGA gain.

000 = 1.15 (default)

001 = 2.3

010 = 3.25

011 = 4.6

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